/**
 * \file IfxGeth_bf.h
 * \brief
 * \copyright Copyright (c) 2019 Infineon Technologies AG. All rights reserved.
 *
 *
 * Version: TC37xPD_UM_V1.2.0.R0
 * Specification: TC3xx User Manual V1.2.0
 * MAY BE CHANGED BY USER [yes/no]: No
 *
 *                                 IMPORTANT NOTICE
 *
 *
 * Use of this file is subject to the terms of use agreed between (i) you or 
 * the company in which ordinary course of business you are acting and (ii) 
 * Infineon Technologies AG or its licensees. If and as long as no such 
 * terms of use are agreed, use of this file is subject to following:


 * Boost Software License - Version 1.0 - August 17th, 2003

 * Permission is hereby granted, free of charge, to any person or 
 * organization obtaining a copy of the software and accompanying 
 * documentation covered by this license (the "Software") to use, reproduce,
 * display, distribute, execute, and transmit the Software, and to prepare
 * derivative works of the Software, and to permit third-parties to whom the 
 * Software is furnished to do so, all subject to the following:

 * The copyright notices in the Software and this entire statement, including
 * the above license grant, this restriction and the following disclaimer, must
 * be included in all copies of the Software, in whole or in part, and all
 * derivative works of the Software, unless such copies or derivative works are
 * solely in the form of machine-executable object code generated by a source
 * language processor.

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
 * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE 
 * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * \defgroup IfxSfr_Geth_Registers_BitfieldsMask Bitfields mask and offset
 * \ingroup IfxSfr_Geth_Registers
 * 
 */
#ifndef IFXGETH_BF_H
#define IFXGETH_BF_H 1

/******************************************************************************/

/******************************************************************************/

/** \addtogroup IfxSfr_Geth_Registers_BitfieldsMask
 * \{  */
/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.RE */
#define IFX_GETH_MAC_CONFIGURATION_RE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.RE */
#define IFX_GETH_MAC_CONFIGURATION_RE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.RE */
#define IFX_GETH_MAC_CONFIGURATION_RE_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.TE */
#define IFX_GETH_MAC_CONFIGURATION_TE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.TE */
#define IFX_GETH_MAC_CONFIGURATION_TE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.TE */
#define IFX_GETH_MAC_CONFIGURATION_TE_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.PRELEN */
#define IFX_GETH_MAC_CONFIGURATION_PRELEN_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.PRELEN */
#define IFX_GETH_MAC_CONFIGURATION_PRELEN_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.PRELEN */
#define IFX_GETH_MAC_CONFIGURATION_PRELEN_OFF (2u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.DC */
#define IFX_GETH_MAC_CONFIGURATION_DC_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.DC */
#define IFX_GETH_MAC_CONFIGURATION_DC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.DC */
#define IFX_GETH_MAC_CONFIGURATION_DC_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.BL */
#define IFX_GETH_MAC_CONFIGURATION_BL_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.BL */
#define IFX_GETH_MAC_CONFIGURATION_BL_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.BL */
#define IFX_GETH_MAC_CONFIGURATION_BL_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.DR */
#define IFX_GETH_MAC_CONFIGURATION_DR_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.DR */
#define IFX_GETH_MAC_CONFIGURATION_DR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.DR */
#define IFX_GETH_MAC_CONFIGURATION_DR_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.DCRS */
#define IFX_GETH_MAC_CONFIGURATION_DCRS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.DCRS */
#define IFX_GETH_MAC_CONFIGURATION_DCRS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.DCRS */
#define IFX_GETH_MAC_CONFIGURATION_DCRS_OFF (9u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.DO */
#define IFX_GETH_MAC_CONFIGURATION_DO_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.DO */
#define IFX_GETH_MAC_CONFIGURATION_DO_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.DO */
#define IFX_GETH_MAC_CONFIGURATION_DO_OFF (10u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.ECRSFD */
#define IFX_GETH_MAC_CONFIGURATION_ECRSFD_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.ECRSFD */
#define IFX_GETH_MAC_CONFIGURATION_ECRSFD_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.ECRSFD */
#define IFX_GETH_MAC_CONFIGURATION_ECRSFD_OFF (11u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.LM */
#define IFX_GETH_MAC_CONFIGURATION_LM_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.LM */
#define IFX_GETH_MAC_CONFIGURATION_LM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.LM */
#define IFX_GETH_MAC_CONFIGURATION_LM_OFF (12u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.DM */
#define IFX_GETH_MAC_CONFIGURATION_DM_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.DM */
#define IFX_GETH_MAC_CONFIGURATION_DM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.DM */
#define IFX_GETH_MAC_CONFIGURATION_DM_OFF (13u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.FES */
#define IFX_GETH_MAC_CONFIGURATION_FES_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.FES */
#define IFX_GETH_MAC_CONFIGURATION_FES_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.FES */
#define IFX_GETH_MAC_CONFIGURATION_FES_OFF (14u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.PS */
#define IFX_GETH_MAC_CONFIGURATION_PS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.PS */
#define IFX_GETH_MAC_CONFIGURATION_PS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.PS */
#define IFX_GETH_MAC_CONFIGURATION_PS_OFF (15u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.JE */
#define IFX_GETH_MAC_CONFIGURATION_JE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.JE */
#define IFX_GETH_MAC_CONFIGURATION_JE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.JE */
#define IFX_GETH_MAC_CONFIGURATION_JE_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.JD */
#define IFX_GETH_MAC_CONFIGURATION_JD_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.JD */
#define IFX_GETH_MAC_CONFIGURATION_JD_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.JD */
#define IFX_GETH_MAC_CONFIGURATION_JD_OFF (17u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.BE */
#define IFX_GETH_MAC_CONFIGURATION_BE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.BE */
#define IFX_GETH_MAC_CONFIGURATION_BE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.BE */
#define IFX_GETH_MAC_CONFIGURATION_BE_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.WD */
#define IFX_GETH_MAC_CONFIGURATION_WD_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.WD */
#define IFX_GETH_MAC_CONFIGURATION_WD_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.WD */
#define IFX_GETH_MAC_CONFIGURATION_WD_OFF (19u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.ACS */
#define IFX_GETH_MAC_CONFIGURATION_ACS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.ACS */
#define IFX_GETH_MAC_CONFIGURATION_ACS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.ACS */
#define IFX_GETH_MAC_CONFIGURATION_ACS_OFF (20u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.CST */
#define IFX_GETH_MAC_CONFIGURATION_CST_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.CST */
#define IFX_GETH_MAC_CONFIGURATION_CST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.CST */
#define IFX_GETH_MAC_CONFIGURATION_CST_OFF (21u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.S2KP */
#define IFX_GETH_MAC_CONFIGURATION_S2KP_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.S2KP */
#define IFX_GETH_MAC_CONFIGURATION_S2KP_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.S2KP */
#define IFX_GETH_MAC_CONFIGURATION_S2KP_OFF (22u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.GPSLCE */
#define IFX_GETH_MAC_CONFIGURATION_GPSLCE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.GPSLCE */
#define IFX_GETH_MAC_CONFIGURATION_GPSLCE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.GPSLCE */
#define IFX_GETH_MAC_CONFIGURATION_GPSLCE_OFF (23u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.IPG */
#define IFX_GETH_MAC_CONFIGURATION_IPG_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.IPG */
#define IFX_GETH_MAC_CONFIGURATION_IPG_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.IPG */
#define IFX_GETH_MAC_CONFIGURATION_IPG_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.IPC */
#define IFX_GETH_MAC_CONFIGURATION_IPC_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.IPC */
#define IFX_GETH_MAC_CONFIGURATION_IPC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.IPC */
#define IFX_GETH_MAC_CONFIGURATION_IPC_OFF (27u)

/** \brief Length for Ifx_GETH_MAC_CONFIGURATION_Bits.SARC */
#define IFX_GETH_MAC_CONFIGURATION_SARC_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_CONFIGURATION_Bits.SARC */
#define IFX_GETH_MAC_CONFIGURATION_SARC_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_CONFIGURATION_Bits.SARC */
#define IFX_GETH_MAC_CONFIGURATION_SARC_OFF (28u)

/** \brief Length for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.GPSL */
#define IFX_GETH_MAC_EXT_CONFIGURATION_GPSL_LEN (14u)

/** \brief Mask for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.GPSL */
#define IFX_GETH_MAC_EXT_CONFIGURATION_GPSL_MSK (0x3fffu)

/** \brief Offset for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.GPSL */
#define IFX_GETH_MAC_EXT_CONFIGURATION_GPSL_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.DCRCC */
#define IFX_GETH_MAC_EXT_CONFIGURATION_DCRCC_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.DCRCC */
#define IFX_GETH_MAC_EXT_CONFIGURATION_DCRCC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.DCRCC */
#define IFX_GETH_MAC_EXT_CONFIGURATION_DCRCC_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.SPEN */
#define IFX_GETH_MAC_EXT_CONFIGURATION_SPEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.SPEN */
#define IFX_GETH_MAC_EXT_CONFIGURATION_SPEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.SPEN */
#define IFX_GETH_MAC_EXT_CONFIGURATION_SPEN_OFF (17u)

/** \brief Length for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.USP */
#define IFX_GETH_MAC_EXT_CONFIGURATION_USP_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.USP */
#define IFX_GETH_MAC_EXT_CONFIGURATION_USP_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.USP */
#define IFX_GETH_MAC_EXT_CONFIGURATION_USP_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.HDSMS */
#define IFX_GETH_MAC_EXT_CONFIGURATION_HDSMS_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.HDSMS */
#define IFX_GETH_MAC_EXT_CONFIGURATION_HDSMS_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.HDSMS */
#define IFX_GETH_MAC_EXT_CONFIGURATION_HDSMS_OFF (20u)

/** \brief Length for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.EIPGEN */
#define IFX_GETH_MAC_EXT_CONFIGURATION_EIPGEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.EIPGEN */
#define IFX_GETH_MAC_EXT_CONFIGURATION_EIPGEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.EIPGEN */
#define IFX_GETH_MAC_EXT_CONFIGURATION_EIPGEN_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.EIPG */
#define IFX_GETH_MAC_EXT_CONFIGURATION_EIPG_LEN (5u)

/** \brief Mask for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.EIPG */
#define IFX_GETH_MAC_EXT_CONFIGURATION_EIPG_MSK (0x1fu)

/** \brief Offset for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.EIPG */
#define IFX_GETH_MAC_EXT_CONFIGURATION_EIPG_OFF (25u)

/** \brief Length for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.FHE */
#define IFX_GETH_MAC_EXT_CONFIGURATION_FHE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.FHE */
#define IFX_GETH_MAC_EXT_CONFIGURATION_FHE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_EXT_CONFIGURATION_Bits.FHE */
#define IFX_GETH_MAC_EXT_CONFIGURATION_FHE_OFF (31u)

/** \brief Length for Ifx_GETH_MAC_PACKET_FILTER_Bits.PR */
#define IFX_GETH_MAC_PACKET_FILTER_PR_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PACKET_FILTER_Bits.PR */
#define IFX_GETH_MAC_PACKET_FILTER_PR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PACKET_FILTER_Bits.PR */
#define IFX_GETH_MAC_PACKET_FILTER_PR_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_PACKET_FILTER_Bits.DAIF */
#define IFX_GETH_MAC_PACKET_FILTER_DAIF_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PACKET_FILTER_Bits.DAIF */
#define IFX_GETH_MAC_PACKET_FILTER_DAIF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PACKET_FILTER_Bits.DAIF */
#define IFX_GETH_MAC_PACKET_FILTER_DAIF_OFF (3u)

/** \brief Length for Ifx_GETH_MAC_PACKET_FILTER_Bits.PM */
#define IFX_GETH_MAC_PACKET_FILTER_PM_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PACKET_FILTER_Bits.PM */
#define IFX_GETH_MAC_PACKET_FILTER_PM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PACKET_FILTER_Bits.PM */
#define IFX_GETH_MAC_PACKET_FILTER_PM_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_PACKET_FILTER_Bits.DBF */
#define IFX_GETH_MAC_PACKET_FILTER_DBF_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PACKET_FILTER_Bits.DBF */
#define IFX_GETH_MAC_PACKET_FILTER_DBF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PACKET_FILTER_Bits.DBF */
#define IFX_GETH_MAC_PACKET_FILTER_DBF_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_PACKET_FILTER_Bits.PCF */
#define IFX_GETH_MAC_PACKET_FILTER_PCF_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_PACKET_FILTER_Bits.PCF */
#define IFX_GETH_MAC_PACKET_FILTER_PCF_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_PACKET_FILTER_Bits.PCF */
#define IFX_GETH_MAC_PACKET_FILTER_PCF_OFF (6u)

/** \brief Length for Ifx_GETH_MAC_PACKET_FILTER_Bits.SAIF */
#define IFX_GETH_MAC_PACKET_FILTER_SAIF_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PACKET_FILTER_Bits.SAIF */
#define IFX_GETH_MAC_PACKET_FILTER_SAIF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PACKET_FILTER_Bits.SAIF */
#define IFX_GETH_MAC_PACKET_FILTER_SAIF_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_PACKET_FILTER_Bits.SAF */
#define IFX_GETH_MAC_PACKET_FILTER_SAF_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PACKET_FILTER_Bits.SAF */
#define IFX_GETH_MAC_PACKET_FILTER_SAF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PACKET_FILTER_Bits.SAF */
#define IFX_GETH_MAC_PACKET_FILTER_SAF_OFF (9u)

/** \brief Length for Ifx_GETH_MAC_PACKET_FILTER_Bits.VTFE */
#define IFX_GETH_MAC_PACKET_FILTER_VTFE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PACKET_FILTER_Bits.VTFE */
#define IFX_GETH_MAC_PACKET_FILTER_VTFE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PACKET_FILTER_Bits.VTFE */
#define IFX_GETH_MAC_PACKET_FILTER_VTFE_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_PACKET_FILTER_Bits.RA */
#define IFX_GETH_MAC_PACKET_FILTER_RA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PACKET_FILTER_Bits.RA */
#define IFX_GETH_MAC_PACKET_FILTER_RA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PACKET_FILTER_Bits.RA */
#define IFX_GETH_MAC_PACKET_FILTER_RA_OFF (31u)

/** \brief Length for Ifx_GETH_MAC_WATCHDOG_TIMEOUT_Bits.WTO */
#define IFX_GETH_MAC_WATCHDOG_TIMEOUT_WTO_LEN (4u)

/** \brief Mask for Ifx_GETH_MAC_WATCHDOG_TIMEOUT_Bits.WTO */
#define IFX_GETH_MAC_WATCHDOG_TIMEOUT_WTO_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MAC_WATCHDOG_TIMEOUT_Bits.WTO */
#define IFX_GETH_MAC_WATCHDOG_TIMEOUT_WTO_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_WATCHDOG_TIMEOUT_Bits.PWE */
#define IFX_GETH_MAC_WATCHDOG_TIMEOUT_PWE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_WATCHDOG_TIMEOUT_Bits.PWE */
#define IFX_GETH_MAC_WATCHDOG_TIMEOUT_PWE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_WATCHDOG_TIMEOUT_Bits.PWE */
#define IFX_GETH_MAC_WATCHDOG_TIMEOUT_PWE_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.OB */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_OB_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.OB */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_OB_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.OB */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_OB_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.CT */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_CT_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.CT */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_CT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.CT */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_CT_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.OFS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_OFS_LEN (5u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.OFS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_OFS_MSK (0x1fu)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.OFS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_OFS_OFF (2u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.VTIM */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_VTIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.VTIM */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_VTIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.VTIM */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_VTIM_OFF (17u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.ESVL */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_ESVL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.ESVL */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_ESVL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.ESVL */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_ESVL_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EVLS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EVLS_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EVLS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EVLS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EVLS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EVLS_OFF (21u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EVLRXS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EVLRXS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EVLRXS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EVLRXS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EVLRXS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EVLRXS_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.VTHM */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_VTHM_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.VTHM */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_VTHM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.VTHM */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_VTHM_OFF (25u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EDVLP */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EDVLP_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EDVLP */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EDVLP_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EDVLP */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EDVLP_OFF (26u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.RES_27 */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_RES_27_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.RES_27 */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_RES_27_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.RES_27 */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_RES_27_OFF (27u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EIVLS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EIVLS_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EIVLS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EIVLS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EIVLS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EIVLS_OFF (28u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EIVLRXS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EIVLRXS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EIVLRXS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EIVLRXS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_CTRL_Bits.EIVLRXS */
#define IFX_GETH_MAC_VLAN_TAG_CTRL_EIVLRXS_OFF (31u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.VID */
#define IFX_GETH_MAC_VLAN_TAG_DATA_VID_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.VID */
#define IFX_GETH_MAC_VLAN_TAG_DATA_VID_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.VID */
#define IFX_GETH_MAC_VLAN_TAG_DATA_VID_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.VEN */
#define IFX_GETH_MAC_VLAN_TAG_DATA_VEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.VEN */
#define IFX_GETH_MAC_VLAN_TAG_DATA_VEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.VEN */
#define IFX_GETH_MAC_VLAN_TAG_DATA_VEN_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.ETV */
#define IFX_GETH_MAC_VLAN_TAG_DATA_ETV_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.ETV */
#define IFX_GETH_MAC_VLAN_TAG_DATA_ETV_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.ETV */
#define IFX_GETH_MAC_VLAN_TAG_DATA_ETV_OFF (17u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.DOVLTC */
#define IFX_GETH_MAC_VLAN_TAG_DATA_DOVLTC_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.DOVLTC */
#define IFX_GETH_MAC_VLAN_TAG_DATA_DOVLTC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.DOVLTC */
#define IFX_GETH_MAC_VLAN_TAG_DATA_DOVLTC_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.ERSVLM */
#define IFX_GETH_MAC_VLAN_TAG_DATA_ERSVLM_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.ERSVLM */
#define IFX_GETH_MAC_VLAN_TAG_DATA_ERSVLM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.ERSVLM */
#define IFX_GETH_MAC_VLAN_TAG_DATA_ERSVLM_OFF (19u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.ERIVLT */
#define IFX_GETH_MAC_VLAN_TAG_DATA_ERIVLT_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.ERIVLT */
#define IFX_GETH_MAC_VLAN_TAG_DATA_ERIVLT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.ERIVLT */
#define IFX_GETH_MAC_VLAN_TAG_DATA_ERIVLT_OFF (20u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.DMACHEN */
#define IFX_GETH_MAC_VLAN_TAG_DATA_DMACHEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.DMACHEN */
#define IFX_GETH_MAC_VLAN_TAG_DATA_DMACHEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.DMACHEN */
#define IFX_GETH_MAC_VLAN_TAG_DATA_DMACHEN_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.DMACHN */
#define IFX_GETH_MAC_VLAN_TAG_DATA_DMACHN_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.DMACHN */
#define IFX_GETH_MAC_VLAN_TAG_DATA_DMACHN_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_DATA_Bits.DMACHN */
#define IFX_GETH_MAC_VLAN_TAG_DATA_DMACHN_OFF (25u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.VID */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_VID_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.VID */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_VID_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.VID */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_VID_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.VEN */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_VEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.VEN */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_VEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.VEN */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_VEN_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.ETV */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_ETV_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.ETV */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_ETV_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.ETV */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_ETV_OFF (17u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.DOVLTC */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_DOVLTC_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.DOVLTC */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_DOVLTC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.DOVLTC */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_DOVLTC_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.ERSVLM */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_ERSVLM_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.ERSVLM */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_ERSVLM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.ERSVLM */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_ERSVLM_OFF (19u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.ERIVLT */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_ERIVLT_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.ERIVLT */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_ERIVLT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.ERIVLT */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_ERIVLT_OFF (20u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.DMACHEN */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_DMACHEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.DMACHEN */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_DMACHEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.DMACHEN */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_DMACHEN_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.DMACHN */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_DMACHN_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.DMACHN */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_DMACHN_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_TAG_FILTER_Bits.DMACHN */
#define IFX_GETH_MAC_VLAN_TAG_FILTER_DMACHN_OFF (25u)

/** \brief Length for Ifx_GETH_MAC_VLAN_HASH_TABLE_Bits.VLHT */
#define IFX_GETH_MAC_VLAN_HASH_TABLE_VLHT_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_HASH_TABLE_Bits.VLHT */
#define IFX_GETH_MAC_VLAN_HASH_TABLE_VLHT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_VLAN_HASH_TABLE_Bits.VLHT */
#define IFX_GETH_MAC_VLAN_HASH_TABLE_VLHT_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_VLAN_INCL_Bits.VLT */
#define IFX_GETH_MAC_VLAN_INCL_VLT_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_INCL_Bits.VLT */
#define IFX_GETH_MAC_VLAN_INCL_VLT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_VLAN_INCL_Bits.VLT */
#define IFX_GETH_MAC_VLAN_INCL_VLT_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_VLAN_INCL_Bits.VLC */
#define IFX_GETH_MAC_VLAN_INCL_VLC_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_INCL_Bits.VLC */
#define IFX_GETH_MAC_VLAN_INCL_VLC_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_INCL_Bits.VLC */
#define IFX_GETH_MAC_VLAN_INCL_VLC_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_VLAN_INCL_Bits.VLP */
#define IFX_GETH_MAC_VLAN_INCL_VLP_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_INCL_Bits.VLP */
#define IFX_GETH_MAC_VLAN_INCL_VLP_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_INCL_Bits.VLP */
#define IFX_GETH_MAC_VLAN_INCL_VLP_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_VLAN_INCL_Bits.CSVL */
#define IFX_GETH_MAC_VLAN_INCL_CSVL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_INCL_Bits.CSVL */
#define IFX_GETH_MAC_VLAN_INCL_CSVL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_INCL_Bits.CSVL */
#define IFX_GETH_MAC_VLAN_INCL_CSVL_OFF (19u)

/** \brief Length for Ifx_GETH_MAC_VLAN_INCL_Bits.VLTI */
#define IFX_GETH_MAC_VLAN_INCL_VLTI_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_INCL_Bits.VLTI */
#define IFX_GETH_MAC_VLAN_INCL_VLTI_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_INCL_Bits.VLTI */
#define IFX_GETH_MAC_VLAN_INCL_VLTI_OFF (20u)

/** \brief Length for Ifx_GETH_MAC_VLAN_INCL_Bits.CBTI */
#define IFX_GETH_MAC_VLAN_INCL_CBTI_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_INCL_Bits.CBTI */
#define IFX_GETH_MAC_VLAN_INCL_CBTI_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_INCL_Bits.CBTI */
#define IFX_GETH_MAC_VLAN_INCL_CBTI_OFF (21u)

/** \brief Length for Ifx_GETH_MAC_VLAN_INCL_Bits.ADDR */
#define IFX_GETH_MAC_VLAN_INCL_ADDR_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_INCL_Bits.ADDR */
#define IFX_GETH_MAC_VLAN_INCL_ADDR_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_INCL_Bits.ADDR */
#define IFX_GETH_MAC_VLAN_INCL_ADDR_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_VLAN_INCL_Bits.RDWR */
#define IFX_GETH_MAC_VLAN_INCL_RDWR_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_INCL_Bits.RDWR */
#define IFX_GETH_MAC_VLAN_INCL_RDWR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_INCL_Bits.RDWR */
#define IFX_GETH_MAC_VLAN_INCL_RDWR_OFF (30u)

/** \brief Length for Ifx_GETH_MAC_VLAN_INCL_Bits.BUSY */
#define IFX_GETH_MAC_VLAN_INCL_BUSY_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_INCL_Bits.BUSY */
#define IFX_GETH_MAC_VLAN_INCL_BUSY_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_INCL_Bits.BUSY */
#define IFX_GETH_MAC_VLAN_INCL_BUSY_OFF (31u)

/** \brief Length for Ifx_GETH_MAC_VLAN_INCL_Q_Bits.VLT */
#define IFX_GETH_MAC_VLAN_INCL_Q_VLT_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_INCL_Q_Bits.VLT */
#define IFX_GETH_MAC_VLAN_INCL_Q_VLT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_VLAN_INCL_Q_Bits.VLT */
#define IFX_GETH_MAC_VLAN_INCL_Q_VLT_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_VLAN_INCL_Q_Bits.CSVL */
#define IFX_GETH_MAC_VLAN_INCL_Q_CSVL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_VLAN_INCL_Q_Bits.CSVL */
#define IFX_GETH_MAC_VLAN_INCL_Q_CSVL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_VLAN_INCL_Q_Bits.CSVL */
#define IFX_GETH_MAC_VLAN_INCL_Q_CSVL_OFF (19u)

/** \brief Length for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLT */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLT_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLT */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLT */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLT_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLC */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLC_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLC */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLC_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLC */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLC_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLP */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLP_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLP */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLP_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLP */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLP_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.CSVL */
#define IFX_GETH_MAC_INNER_VLAN_INCL_CSVL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.CSVL */
#define IFX_GETH_MAC_INNER_VLAN_INCL_CSVL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.CSVL */
#define IFX_GETH_MAC_INNER_VLAN_INCL_CSVL_OFF (19u)

/** \brief Length for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLTI */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLTI_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLTI */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLTI_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INNER_VLAN_INCL_Bits.VLTI */
#define IFX_GETH_MAC_INNER_VLAN_INCL_VLTI_OFF (20u)

/** \brief Length for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.FCB_BPA */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.FCB_BPA */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.FCB_BPA */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_FCB_BPA_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.TFE */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_TFE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.TFE */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_TFE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.TFE */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_TFE_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.PLT */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_PLT_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.PLT */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_PLT_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.PLT */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_PLT_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.DZPQ */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_DZPQ_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.DZPQ */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_DZPQ_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.DZPQ */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_DZPQ_OFF (7u)

/** \brief Length for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.PT */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_PT_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.PT */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_PT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_Q0_TX_FLOW_CTRL_Bits.PT */
#define IFX_GETH_MAC_Q0_TX_FLOW_CTRL_PT_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_RX_FLOW_CTRL_Bits.RFE */
#define IFX_GETH_MAC_RX_FLOW_CTRL_RFE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RX_FLOW_CTRL_Bits.RFE */
#define IFX_GETH_MAC_RX_FLOW_CTRL_RFE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RX_FLOW_CTRL_Bits.RFE */
#define IFX_GETH_MAC_RX_FLOW_CTRL_RFE_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_RX_FLOW_CTRL_Bits.UP */
#define IFX_GETH_MAC_RX_FLOW_CTRL_UP_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RX_FLOW_CTRL_Bits.UP */
#define IFX_GETH_MAC_RX_FLOW_CTRL_UP_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RX_FLOW_CTRL_Bits.UP */
#define IFX_GETH_MAC_RX_FLOW_CTRL_UP_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL4_Bits.UFFQE */
#define IFX_GETH_MAC_RXQ_CTRL4_UFFQE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL4_Bits.UFFQE */
#define IFX_GETH_MAC_RXQ_CTRL4_UFFQE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL4_Bits.UFFQE */
#define IFX_GETH_MAC_RXQ_CTRL4_UFFQE_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL4_Bits.UFFQ */
#define IFX_GETH_MAC_RXQ_CTRL4_UFFQ_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL4_Bits.UFFQ */
#define IFX_GETH_MAC_RXQ_CTRL4_UFFQ_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL4_Bits.UFFQ */
#define IFX_GETH_MAC_RXQ_CTRL4_UFFQ_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL4_Bits.MFFQE */
#define IFX_GETH_MAC_RXQ_CTRL4_MFFQE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL4_Bits.MFFQE */
#define IFX_GETH_MAC_RXQ_CTRL4_MFFQE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL4_Bits.MFFQE */
#define IFX_GETH_MAC_RXQ_CTRL4_MFFQE_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL4_Bits.MFFQ */
#define IFX_GETH_MAC_RXQ_CTRL4_MFFQ_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL4_Bits.MFFQ */
#define IFX_GETH_MAC_RXQ_CTRL4_MFFQ_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL4_Bits.MFFQ */
#define IFX_GETH_MAC_RXQ_CTRL4_MFFQ_OFF (9u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL4_Bits.VFFQE */
#define IFX_GETH_MAC_RXQ_CTRL4_VFFQE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL4_Bits.VFFQE */
#define IFX_GETH_MAC_RXQ_CTRL4_VFFQE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL4_Bits.VFFQE */
#define IFX_GETH_MAC_RXQ_CTRL4_VFFQE_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL4_Bits.VFFQ */
#define IFX_GETH_MAC_RXQ_CTRL4_VFFQ_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL4_Bits.VFFQ */
#define IFX_GETH_MAC_RXQ_CTRL4_VFFQ_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL4_Bits.VFFQ */
#define IFX_GETH_MAC_RXQ_CTRL4_VFFQ_OFF (17u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ0EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ0EN_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ0EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ0EN_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ0EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ0EN_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ1EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ1EN_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ1EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ1EN_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ1EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ1EN_OFF (2u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ2EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ2EN_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ2EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ2EN_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ2EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ2EN_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ3EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ3EN_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ3EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ3EN_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL0_Bits.RXQ3EN */
#define IFX_GETH_MAC_RXQ_CTRL0_RXQ3EN_OFF (6u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL1_Bits.AVCPQ */
#define IFX_GETH_MAC_RXQ_CTRL1_AVCPQ_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL1_Bits.AVCPQ */
#define IFX_GETH_MAC_RXQ_CTRL1_AVCPQ_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL1_Bits.AVCPQ */
#define IFX_GETH_MAC_RXQ_CTRL1_AVCPQ_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL1_Bits.PTPQ */
#define IFX_GETH_MAC_RXQ_CTRL1_PTPQ_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL1_Bits.PTPQ */
#define IFX_GETH_MAC_RXQ_CTRL1_PTPQ_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL1_Bits.PTPQ */
#define IFX_GETH_MAC_RXQ_CTRL1_PTPQ_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL1_Bits.UPQ */
#define IFX_GETH_MAC_RXQ_CTRL1_UPQ_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL1_Bits.UPQ */
#define IFX_GETH_MAC_RXQ_CTRL1_UPQ_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL1_Bits.UPQ */
#define IFX_GETH_MAC_RXQ_CTRL1_UPQ_OFF (12u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL1_Bits.MCBCQ */
#define IFX_GETH_MAC_RXQ_CTRL1_MCBCQ_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL1_Bits.MCBCQ */
#define IFX_GETH_MAC_RXQ_CTRL1_MCBCQ_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL1_Bits.MCBCQ */
#define IFX_GETH_MAC_RXQ_CTRL1_MCBCQ_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL1_Bits.MCBCQEN */
#define IFX_GETH_MAC_RXQ_CTRL1_MCBCQEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL1_Bits.MCBCQEN */
#define IFX_GETH_MAC_RXQ_CTRL1_MCBCQEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL1_Bits.MCBCQEN */
#define IFX_GETH_MAC_RXQ_CTRL1_MCBCQEN_OFF (20u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL1_Bits.TACPQE */
#define IFX_GETH_MAC_RXQ_CTRL1_TACPQE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL1_Bits.TACPQE */
#define IFX_GETH_MAC_RXQ_CTRL1_TACPQE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL1_Bits.TACPQE */
#define IFX_GETH_MAC_RXQ_CTRL1_TACPQE_OFF (21u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL1_Bits.TPQC */
#define IFX_GETH_MAC_RXQ_CTRL1_TPQC_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL1_Bits.TPQC */
#define IFX_GETH_MAC_RXQ_CTRL1_TPQC_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL1_Bits.TPQC */
#define IFX_GETH_MAC_RXQ_CTRL1_TPQC_OFF (22u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ0 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ0_LEN (8u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ0 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ0_MSK (0xffu)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ0 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ0_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ1 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ1_LEN (8u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ1 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ1_MSK (0xffu)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ1 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ1_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ2 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ2_LEN (8u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ2 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ2_MSK (0xffu)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ2 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ2_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ3 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ3_LEN (8u)

/** \brief Mask for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ3 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ3_MSK (0xffu)

/** \brief Offset for Ifx_GETH_MAC_RXQ_CTRL2_Bits.PSRQ3 */
#define IFX_GETH_MAC_RXQ_CTRL2_PSRQ3_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.RGSMIIIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_RGSMIIIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.RGSMIIIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_RGSMIIIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.RGSMIIIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_RGSMIIIS_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.PHYIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_PHYIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.PHYIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_PHYIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.PHYIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_PHYIS_OFF (3u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.PMTIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_PMTIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.PMTIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_PMTIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.PMTIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_PMTIS_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.LPIIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_LPIIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.LPIIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_LPIIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.LPIIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_LPIIS_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCIS_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCRXIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCRXIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCRXIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCRXIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCRXIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCRXIS_OFF (9u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCTXIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCTXIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCTXIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCTXIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCTXIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCTXIS_OFF (10u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCRXIPIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCRXIPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCRXIPIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCRXIPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MMCRXIPIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MMCRXIPIS_OFF (11u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.TSIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_TSIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.TSIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_TSIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.TSIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_TSIS_OFF (12u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.TXSTSIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_TXSTSIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.TXSTSIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_TXSTSIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.TXSTSIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_TXSTSIS_OFF (13u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.RXSTSIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_RXSTSIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.RXSTSIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_RXSTSIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.RXSTSIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_RXSTSIS_OFF (14u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MDIOIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MDIOIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MDIOIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MDIOIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_STATUS_Bits.MDIOIS */
#define IFX_GETH_MAC_INTERRUPT_STATUS_MDIOIS_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.RGSMIIIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_RGSMIIIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.RGSMIIIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_RGSMIIIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.RGSMIIIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_RGSMIIIE_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.PHYIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_PHYIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.PHYIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_PHYIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.PHYIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_PHYIE_OFF (3u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.PMTIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_PMTIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.PMTIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_PMTIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.PMTIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_PMTIE_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.LPIIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_LPIIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.LPIIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_LPIIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.LPIIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_LPIIE_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.TSIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_TSIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.TSIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_TSIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.TSIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_TSIE_OFF (12u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.TXSTSIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_TXSTSIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.TXSTSIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_TXSTSIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.TXSTSIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_TXSTSIE_OFF (13u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.RXSTSIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_RXSTSIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.RXSTSIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_RXSTSIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.RXSTSIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_RXSTSIE_OFF (14u)

/** \brief Length for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.MDIOIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_MDIOIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.MDIOIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_MDIOIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_INTERRUPT_ENABLE_Bits.MDIOIE */
#define IFX_GETH_MAC_INTERRUPT_ENABLE_MDIOIE_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_RX_TX_STATUS_Bits.TJT */
#define IFX_GETH_MAC_RX_TX_STATUS_TJT_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RX_TX_STATUS_Bits.TJT */
#define IFX_GETH_MAC_RX_TX_STATUS_TJT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RX_TX_STATUS_Bits.TJT */
#define IFX_GETH_MAC_RX_TX_STATUS_TJT_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_RX_TX_STATUS_Bits.NCARR */
#define IFX_GETH_MAC_RX_TX_STATUS_NCARR_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RX_TX_STATUS_Bits.NCARR */
#define IFX_GETH_MAC_RX_TX_STATUS_NCARR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RX_TX_STATUS_Bits.NCARR */
#define IFX_GETH_MAC_RX_TX_STATUS_NCARR_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_RX_TX_STATUS_Bits.LCARR */
#define IFX_GETH_MAC_RX_TX_STATUS_LCARR_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RX_TX_STATUS_Bits.LCARR */
#define IFX_GETH_MAC_RX_TX_STATUS_LCARR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RX_TX_STATUS_Bits.LCARR */
#define IFX_GETH_MAC_RX_TX_STATUS_LCARR_OFF (2u)

/** \brief Length for Ifx_GETH_MAC_RX_TX_STATUS_Bits.EXDEF */
#define IFX_GETH_MAC_RX_TX_STATUS_EXDEF_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RX_TX_STATUS_Bits.EXDEF */
#define IFX_GETH_MAC_RX_TX_STATUS_EXDEF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RX_TX_STATUS_Bits.EXDEF */
#define IFX_GETH_MAC_RX_TX_STATUS_EXDEF_OFF (3u)

/** \brief Length for Ifx_GETH_MAC_RX_TX_STATUS_Bits.LCOL */
#define IFX_GETH_MAC_RX_TX_STATUS_LCOL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RX_TX_STATUS_Bits.LCOL */
#define IFX_GETH_MAC_RX_TX_STATUS_LCOL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RX_TX_STATUS_Bits.LCOL */
#define IFX_GETH_MAC_RX_TX_STATUS_LCOL_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_RX_TX_STATUS_Bits.EXCOL */
#define IFX_GETH_MAC_RX_TX_STATUS_EXCOL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RX_TX_STATUS_Bits.EXCOL */
#define IFX_GETH_MAC_RX_TX_STATUS_EXCOL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RX_TX_STATUS_Bits.EXCOL */
#define IFX_GETH_MAC_RX_TX_STATUS_EXCOL_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_RX_TX_STATUS_Bits.RWT */
#define IFX_GETH_MAC_RX_TX_STATUS_RWT_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_RX_TX_STATUS_Bits.RWT */
#define IFX_GETH_MAC_RX_TX_STATUS_RWT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_RX_TX_STATUS_Bits.RWT */
#define IFX_GETH_MAC_RX_TX_STATUS_RWT_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.PWRDWN */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_PWRDWN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.PWRDWN */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_PWRDWN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.PWRDWN */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_PWRDWN_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.MGKPKTEN */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_MGKPKTEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.MGKPKTEN */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.MGKPKTEN */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_MGKPKTEN_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPKTEN */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPKTEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPKTEN */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPKTEN */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPKTEN_OFF (2u)

/** \brief Length for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.MGKPRCVD */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_MGKPRCVD_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.MGKPRCVD */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.MGKPRCVD */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_MGKPRCVD_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPRCVD */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPRCVD_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPRCVD */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPRCVD */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPRCVD_OFF (6u)

/** \brief Length for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.GLBLUCAST */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_GLBLUCAST_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.GLBLUCAST */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.GLBLUCAST */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_GLBLUCAST_OFF (9u)

/** \brief Length for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPFE */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPFE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPFE */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPFE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPFE */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPFE_OFF (10u)

/** \brief Length for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPTR */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPTR_LEN (5u)

/** \brief Mask for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPTR */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPTR_MSK (0x1fu)

/** \brief Offset for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKPTR */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKPTR_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKFILTRST */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKFILTRST_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKFILTRST */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PMT_CONTROL_STATUS_Bits.RWKFILTRST */
#define IFX_GETH_MAC_PMT_CONTROL_STATUS_RWKFILTRST_OFF (31u)

/** \brief Length for Ifx_GETH_MAC_RWK_PACKET_FILTER_Bits.WKUPFRMFTR */
#define IFX_GETH_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_RWK_PACKET_FILTER_Bits.WKUPFRMFTR */
#define IFX_GETH_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_RWK_PACKET_FILTER_Bits.WKUPFRMFTR */
#define IFX_GETH_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_OFF (0u)

/** \brief Length for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter0_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER0_COMMAND_LEN (4u)

/** \brief Mask for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter0_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER0_COMMAND_MSK (0xfu)

/** \brief Offset for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter0_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER0_COMMAND_OFF (0u)

/** \brief Length for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter1_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER1_COMMAND_LEN (4u)

/** \brief Mask for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter1_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER1_COMMAND_MSK (0xfu)

/** \brief Offset for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter1_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER1_COMMAND_OFF (8u)

/** \brief Length for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter2_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER2_COMMAND_LEN (4u)

/** \brief Mask for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter2_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER2_COMMAND_MSK (0xfu)

/** \brief Offset for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter2_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER2_COMMAND_OFF (16u)

/** \brief Length for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter3_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER3_COMMAND_LEN (4u)

/** \brief Mask for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter3_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER3_COMMAND_MSK (0xfu)

/** \brief Offset for Ifx_GETH_RWK_FILTER_COMMAND_0_Bits.Filter3_Command */
#define IFX_GETH_RWK_FILTER_COMMAND_0_FILTER3_COMMAND_OFF (24u)

/** \brief Length for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter0_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER0_OFFSET_LEN (8u)

/** \brief Mask for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter0_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER0_OFFSET_MSK (0xffu)

/** \brief Offset for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter0_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER0_OFFSET_OFF (0u)

/** \brief Length for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter1_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER1_OFFSET_LEN (8u)

/** \brief Mask for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter1_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER1_OFFSET_MSK (0xffu)

/** \brief Offset for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter1_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER1_OFFSET_OFF (8u)

/** \brief Length for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter2_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER2_OFFSET_LEN (8u)

/** \brief Mask for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter2_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER2_OFFSET_MSK (0xffu)

/** \brief Offset for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter2_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER2_OFFSET_OFF (16u)

/** \brief Length for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter3_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER3_OFFSET_LEN (8u)

/** \brief Mask for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter3_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER3_OFFSET_MSK (0xffu)

/** \brief Offset for Ifx_GETH_RWK_FILTER_OFFSET_0_Bits.Filter3_Offset */
#define IFX_GETH_RWK_FILTER_OFFSET_0_FILTER3_OFFSET_OFF (24u)

/** \brief Length for Ifx_GETH_RWK_FILTER_CRC_Bits.Filter0_CRC */
#define IFX_GETH_RWK_FILTER_CRC_FILTER0_CRC_LEN (16u)

/** \brief Mask for Ifx_GETH_RWK_FILTER_CRC_Bits.Filter0_CRC */
#define IFX_GETH_RWK_FILTER_CRC_FILTER0_CRC_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RWK_FILTER_CRC_Bits.Filter0_CRC */
#define IFX_GETH_RWK_FILTER_CRC_FILTER0_CRC_OFF (0u)

/** \brief Length for Ifx_GETH_RWK_FILTER_CRC_Bits.Filter1_CRC */
#define IFX_GETH_RWK_FILTER_CRC_FILTER1_CRC_LEN (16u)

/** \brief Mask for Ifx_GETH_RWK_FILTER_CRC_Bits.Filter1_CRC */
#define IFX_GETH_RWK_FILTER_CRC_FILTER1_CRC_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RWK_FILTER_CRC_Bits.Filter1_CRC */
#define IFX_GETH_RWK_FILTER_CRC_FILTER1_CRC_OFF (16u)

/** \brief Length for Ifx_GETH_RWK_FILTER_BYTE_MASK_Bits.Filteri_Byte_Mask */
#define IFX_GETH_RWK_FILTER_BYTE_MASK_FILTERI_BYTE_MASK_LEN (32u)

/** \brief Mask for Ifx_GETH_RWK_FILTER_BYTE_MASK_Bits.Filteri_Byte_Mask */
#define IFX_GETH_RWK_FILTER_BYTE_MASK_FILTERI_BYTE_MASK_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RWK_FILTER_BYTE_MASK_Bits.Filteri_Byte_Mask */
#define IFX_GETH_RWK_FILTER_BYTE_MASK_FILTERI_BYTE_MASK_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.TLPIEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_TLPIEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.TLPIEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_TLPIEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.TLPIEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_TLPIEN_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.TLPIEX */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_TLPIEX_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.TLPIEX */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_TLPIEX_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.TLPIEX */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_TLPIEX_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.RLPIEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_RLPIEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.RLPIEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_RLPIEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.RLPIEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_RLPIEN_OFF (2u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.RLPIEX */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_RLPIEX_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.RLPIEX */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_RLPIEX_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.RLPIEX */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_RLPIEX_OFF (3u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.TLPIST */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_TLPIST_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.TLPIST */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_TLPIST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.TLPIST */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_TLPIST_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.RLPIST */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_RLPIST_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.RLPIST */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_RLPIST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.RLPIST */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_RLPIST_OFF (9u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPIEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPIEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPIEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPIEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPIEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPIEN_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.PLS */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_PLS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.PLS */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_PLS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.PLS */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_PLS_OFF (17u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.PLSEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_PLSEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.PLSEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_PLSEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.PLSEN */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_PLSEN_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPITXA */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPITXA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPITXA */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPITXA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPITXA */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPITXA_OFF (19u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPIATE */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPIATE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPIATE */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPIATE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPIATE */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPIATE_OFF (20u)

/** \brief Length for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPITCSE */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPITCSE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPITCSE */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPITCSE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_LPI_CONTROL_STATUS_Bits.LPITCSE */
#define IFX_GETH_MAC_LPI_CONTROL_STATUS_LPITCSE_OFF (21u)

/** \brief Length for Ifx_GETH_MAC_LPI_TIMERS_CONTROL_Bits.TWT */
#define IFX_GETH_MAC_LPI_TIMERS_CONTROL_TWT_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_LPI_TIMERS_CONTROL_Bits.TWT */
#define IFX_GETH_MAC_LPI_TIMERS_CONTROL_TWT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_LPI_TIMERS_CONTROL_Bits.TWT */
#define IFX_GETH_MAC_LPI_TIMERS_CONTROL_TWT_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_LPI_TIMERS_CONTROL_Bits.LST */
#define IFX_GETH_MAC_LPI_TIMERS_CONTROL_LST_LEN (10u)

/** \brief Mask for Ifx_GETH_MAC_LPI_TIMERS_CONTROL_Bits.LST */
#define IFX_GETH_MAC_LPI_TIMERS_CONTROL_LST_MSK (0x3ffu)

/** \brief Offset for Ifx_GETH_MAC_LPI_TIMERS_CONTROL_Bits.LST */
#define IFX_GETH_MAC_LPI_TIMERS_CONTROL_LST_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_LPI_ENTRY_TIMER_Bits.LPIET */
#define IFX_GETH_MAC_LPI_ENTRY_TIMER_LPIET_LEN (17u)

/** \brief Mask for Ifx_GETH_MAC_LPI_ENTRY_TIMER_Bits.LPIET */
#define IFX_GETH_MAC_LPI_ENTRY_TIMER_LPIET_MSK (0x1ffffu)

/** \brief Offset for Ifx_GETH_MAC_LPI_ENTRY_TIMER_Bits.LPIET */
#define IFX_GETH_MAC_LPI_ENTRY_TIMER_LPIET_OFF (3u)

/** \brief Length for Ifx_GETH_MAC_1US_TIC_COUNTER_Bits.TIC_1US_CNTR */
#define IFX_GETH_MAC_1US_TIC_COUNTER_TIC_1US_CNTR_LEN (12u)

/** \brief Mask for Ifx_GETH_MAC_1US_TIC_COUNTER_Bits.TIC_1US_CNTR */
#define IFX_GETH_MAC_1US_TIC_COUNTER_TIC_1US_CNTR_MSK (0xfffu)

/** \brief Offset for Ifx_GETH_MAC_1US_TIC_COUNTER_Bits.TIC_1US_CNTR */
#define IFX_GETH_MAC_1US_TIC_COUNTER_TIC_1US_CNTR_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.TC */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_TC_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.TC */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_TC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.TC */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_TC_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LUD */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LUD_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LUD */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LUD_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LUD */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LUD_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LNKMOD */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LNKMOD_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LNKMOD */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LNKMOD */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LNKMOD_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LNKSPEED */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LNKSPEED */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LNKSPEED */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_OFF (17u)

/** \brief Length for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LNKSTS */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LNKSTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LNKSTS */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PHYIF_CONTROL_STATUS_Bits.LNKSTS */
#define IFX_GETH_MAC_PHYIF_CONTROL_STATUS_LNKSTS_OFF (19u)

/** \brief Length for Ifx_GETH_MAC_VERSION_Bits.SNPSVER */
#define IFX_GETH_MAC_VERSION_SNPSVER_LEN (8u)

/** \brief Mask for Ifx_GETH_MAC_VERSION_Bits.SNPSVER */
#define IFX_GETH_MAC_VERSION_SNPSVER_MSK (0xffu)

/** \brief Offset for Ifx_GETH_MAC_VERSION_Bits.SNPSVER */
#define IFX_GETH_MAC_VERSION_SNPSVER_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_VERSION_Bits.USERVER */
#define IFX_GETH_MAC_VERSION_USERVER_LEN (8u)

/** \brief Mask for Ifx_GETH_MAC_VERSION_Bits.USERVER */
#define IFX_GETH_MAC_VERSION_USERVER_MSK (0xffu)

/** \brief Offset for Ifx_GETH_MAC_VERSION_Bits.USERVER */
#define IFX_GETH_MAC_VERSION_USERVER_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_DEBUG_Bits.RPESTS */
#define IFX_GETH_MAC_DEBUG_RPESTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_DEBUG_Bits.RPESTS */
#define IFX_GETH_MAC_DEBUG_RPESTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_DEBUG_Bits.RPESTS */
#define IFX_GETH_MAC_DEBUG_RPESTS_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_DEBUG_Bits.RFCFCSTS */
#define IFX_GETH_MAC_DEBUG_RFCFCSTS_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_DEBUG_Bits.RFCFCSTS */
#define IFX_GETH_MAC_DEBUG_RFCFCSTS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_DEBUG_Bits.RFCFCSTS */
#define IFX_GETH_MAC_DEBUG_RFCFCSTS_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_DEBUG_Bits.TPESTS */
#define IFX_GETH_MAC_DEBUG_TPESTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_DEBUG_Bits.TPESTS */
#define IFX_GETH_MAC_DEBUG_TPESTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_DEBUG_Bits.TPESTS */
#define IFX_GETH_MAC_DEBUG_TPESTS_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_DEBUG_Bits.TFCSTS */
#define IFX_GETH_MAC_DEBUG_TFCSTS_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_DEBUG_Bits.TFCSTS */
#define IFX_GETH_MAC_DEBUG_TFCSTS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_DEBUG_Bits.TFCSTS */
#define IFX_GETH_MAC_DEBUG_TFCSTS_OFF (17u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.MIISEL */
#define IFX_GETH_MAC_HW_FEATURE0_MIISEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.MIISEL */
#define IFX_GETH_MAC_HW_FEATURE0_MIISEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.MIISEL */
#define IFX_GETH_MAC_HW_FEATURE0_MIISEL_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.GMIISEL */
#define IFX_GETH_MAC_HW_FEATURE0_GMIISEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.GMIISEL */
#define IFX_GETH_MAC_HW_FEATURE0_GMIISEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.GMIISEL */
#define IFX_GETH_MAC_HW_FEATURE0_GMIISEL_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.HDSEL */
#define IFX_GETH_MAC_HW_FEATURE0_HDSEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.HDSEL */
#define IFX_GETH_MAC_HW_FEATURE0_HDSEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.HDSEL */
#define IFX_GETH_MAC_HW_FEATURE0_HDSEL_OFF (2u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.PCSSEL */
#define IFX_GETH_MAC_HW_FEATURE0_PCSSEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.PCSSEL */
#define IFX_GETH_MAC_HW_FEATURE0_PCSSEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.PCSSEL */
#define IFX_GETH_MAC_HW_FEATURE0_PCSSEL_OFF (3u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.VLHASH */
#define IFX_GETH_MAC_HW_FEATURE0_VLHASH_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.VLHASH */
#define IFX_GETH_MAC_HW_FEATURE0_VLHASH_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.VLHASH */
#define IFX_GETH_MAC_HW_FEATURE0_VLHASH_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.SMASEL */
#define IFX_GETH_MAC_HW_FEATURE0_SMASEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.SMASEL */
#define IFX_GETH_MAC_HW_FEATURE0_SMASEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.SMASEL */
#define IFX_GETH_MAC_HW_FEATURE0_SMASEL_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.RWKSEL */
#define IFX_GETH_MAC_HW_FEATURE0_RWKSEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.RWKSEL */
#define IFX_GETH_MAC_HW_FEATURE0_RWKSEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.RWKSEL */
#define IFX_GETH_MAC_HW_FEATURE0_RWKSEL_OFF (6u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.MGKSEL */
#define IFX_GETH_MAC_HW_FEATURE0_MGKSEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.MGKSEL */
#define IFX_GETH_MAC_HW_FEATURE0_MGKSEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.MGKSEL */
#define IFX_GETH_MAC_HW_FEATURE0_MGKSEL_OFF (7u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.MMCSEL */
#define IFX_GETH_MAC_HW_FEATURE0_MMCSEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.MMCSEL */
#define IFX_GETH_MAC_HW_FEATURE0_MMCSEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.MMCSEL */
#define IFX_GETH_MAC_HW_FEATURE0_MMCSEL_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.ARPOFFSEL */
#define IFX_GETH_MAC_HW_FEATURE0_ARPOFFSEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.ARPOFFSEL */
#define IFX_GETH_MAC_HW_FEATURE0_ARPOFFSEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.ARPOFFSEL */
#define IFX_GETH_MAC_HW_FEATURE0_ARPOFFSEL_OFF (9u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.TSSEL */
#define IFX_GETH_MAC_HW_FEATURE0_TSSEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.TSSEL */
#define IFX_GETH_MAC_HW_FEATURE0_TSSEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.TSSEL */
#define IFX_GETH_MAC_HW_FEATURE0_TSSEL_OFF (12u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.EEESEL */
#define IFX_GETH_MAC_HW_FEATURE0_EEESEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.EEESEL */
#define IFX_GETH_MAC_HW_FEATURE0_EEESEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.EEESEL */
#define IFX_GETH_MAC_HW_FEATURE0_EEESEL_OFF (13u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.TXCOESEL */
#define IFX_GETH_MAC_HW_FEATURE0_TXCOESEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.TXCOESEL */
#define IFX_GETH_MAC_HW_FEATURE0_TXCOESEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.TXCOESEL */
#define IFX_GETH_MAC_HW_FEATURE0_TXCOESEL_OFF (14u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.RXCOESEL */
#define IFX_GETH_MAC_HW_FEATURE0_RXCOESEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.RXCOESEL */
#define IFX_GETH_MAC_HW_FEATURE0_RXCOESEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.RXCOESEL */
#define IFX_GETH_MAC_HW_FEATURE0_RXCOESEL_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.ADDMACADRSEL */
#define IFX_GETH_MAC_HW_FEATURE0_ADDMACADRSEL_LEN (5u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.ADDMACADRSEL */
#define IFX_GETH_MAC_HW_FEATURE0_ADDMACADRSEL_MSK (0x1fu)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.ADDMACADRSEL */
#define IFX_GETH_MAC_HW_FEATURE0_ADDMACADRSEL_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.MACADR32SEL */
#define IFX_GETH_MAC_HW_FEATURE0_MACADR32SEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.MACADR32SEL */
#define IFX_GETH_MAC_HW_FEATURE0_MACADR32SEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.MACADR32SEL */
#define IFX_GETH_MAC_HW_FEATURE0_MACADR32SEL_OFF (23u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.MACADR64SEL */
#define IFX_GETH_MAC_HW_FEATURE0_MACADR64SEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.MACADR64SEL */
#define IFX_GETH_MAC_HW_FEATURE0_MACADR64SEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.MACADR64SEL */
#define IFX_GETH_MAC_HW_FEATURE0_MACADR64SEL_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.TSSTSSEL */
#define IFX_GETH_MAC_HW_FEATURE0_TSSTSSEL_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.TSSTSSEL */
#define IFX_GETH_MAC_HW_FEATURE0_TSSTSSEL_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.TSSTSSEL */
#define IFX_GETH_MAC_HW_FEATURE0_TSSTSSEL_OFF (25u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.SAVLANINS */
#define IFX_GETH_MAC_HW_FEATURE0_SAVLANINS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.SAVLANINS */
#define IFX_GETH_MAC_HW_FEATURE0_SAVLANINS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.SAVLANINS */
#define IFX_GETH_MAC_HW_FEATURE0_SAVLANINS_OFF (27u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE0_Bits.ACTPHYSEL */
#define IFX_GETH_MAC_HW_FEATURE0_ACTPHYSEL_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE0_Bits.ACTPHYSEL */
#define IFX_GETH_MAC_HW_FEATURE0_ACTPHYSEL_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE0_Bits.ACTPHYSEL */
#define IFX_GETH_MAC_HW_FEATURE0_ACTPHYSEL_OFF (28u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.RXFIFOSIZE */
#define IFX_GETH_MAC_HW_FEATURE1_RXFIFOSIZE_LEN (5u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.RXFIFOSIZE */
#define IFX_GETH_MAC_HW_FEATURE1_RXFIFOSIZE_MSK (0x1fu)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.RXFIFOSIZE */
#define IFX_GETH_MAC_HW_FEATURE1_RXFIFOSIZE_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.SPRAM */
#define IFX_GETH_MAC_HW_FEATURE1_SPRAM_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.SPRAM */
#define IFX_GETH_MAC_HW_FEATURE1_SPRAM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.SPRAM */
#define IFX_GETH_MAC_HW_FEATURE1_SPRAM_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.TXFIFOSIZE */
#define IFX_GETH_MAC_HW_FEATURE1_TXFIFOSIZE_LEN (5u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.TXFIFOSIZE */
#define IFX_GETH_MAC_HW_FEATURE1_TXFIFOSIZE_MSK (0x1fu)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.TXFIFOSIZE */
#define IFX_GETH_MAC_HW_FEATURE1_TXFIFOSIZE_OFF (6u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.OSTEN */
#define IFX_GETH_MAC_HW_FEATURE1_OSTEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.OSTEN */
#define IFX_GETH_MAC_HW_FEATURE1_OSTEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.OSTEN */
#define IFX_GETH_MAC_HW_FEATURE1_OSTEN_OFF (11u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.PTOEN */
#define IFX_GETH_MAC_HW_FEATURE1_PTOEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.PTOEN */
#define IFX_GETH_MAC_HW_FEATURE1_PTOEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.PTOEN */
#define IFX_GETH_MAC_HW_FEATURE1_PTOEN_OFF (12u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.ADVTHWORD */
#define IFX_GETH_MAC_HW_FEATURE1_ADVTHWORD_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.ADVTHWORD */
#define IFX_GETH_MAC_HW_FEATURE1_ADVTHWORD_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.ADVTHWORD */
#define IFX_GETH_MAC_HW_FEATURE1_ADVTHWORD_OFF (13u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.ADDR64 */
#define IFX_GETH_MAC_HW_FEATURE1_ADDR64_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.ADDR64 */
#define IFX_GETH_MAC_HW_FEATURE1_ADDR64_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.ADDR64 */
#define IFX_GETH_MAC_HW_FEATURE1_ADDR64_OFF (14u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.DCBEN */
#define IFX_GETH_MAC_HW_FEATURE1_DCBEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.DCBEN */
#define IFX_GETH_MAC_HW_FEATURE1_DCBEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.DCBEN */
#define IFX_GETH_MAC_HW_FEATURE1_DCBEN_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.SPHEN */
#define IFX_GETH_MAC_HW_FEATURE1_SPHEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.SPHEN */
#define IFX_GETH_MAC_HW_FEATURE1_SPHEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.SPHEN */
#define IFX_GETH_MAC_HW_FEATURE1_SPHEN_OFF (17u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.TSOEN */
#define IFX_GETH_MAC_HW_FEATURE1_TSOEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.TSOEN */
#define IFX_GETH_MAC_HW_FEATURE1_TSOEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.TSOEN */
#define IFX_GETH_MAC_HW_FEATURE1_TSOEN_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.DBGMEMA */
#define IFX_GETH_MAC_HW_FEATURE1_DBGMEMA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.DBGMEMA */
#define IFX_GETH_MAC_HW_FEATURE1_DBGMEMA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.DBGMEMA */
#define IFX_GETH_MAC_HW_FEATURE1_DBGMEMA_OFF (19u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.AVSEL */
#define IFX_GETH_MAC_HW_FEATURE1_AVSEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.AVSEL */
#define IFX_GETH_MAC_HW_FEATURE1_AVSEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.AVSEL */
#define IFX_GETH_MAC_HW_FEATURE1_AVSEL_OFF (20u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.RAVSEL */
#define IFX_GETH_MAC_HW_FEATURE1_RAVSEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.RAVSEL */
#define IFX_GETH_MAC_HW_FEATURE1_RAVSEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.RAVSEL */
#define IFX_GETH_MAC_HW_FEATURE1_RAVSEL_OFF (21u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.POUOST */
#define IFX_GETH_MAC_HW_FEATURE1_POUOST_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.POUOST */
#define IFX_GETH_MAC_HW_FEATURE1_POUOST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.POUOST */
#define IFX_GETH_MAC_HW_FEATURE1_POUOST_OFF (23u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.HASHTBLSZ */
#define IFX_GETH_MAC_HW_FEATURE1_HASHTBLSZ_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.HASHTBLSZ */
#define IFX_GETH_MAC_HW_FEATURE1_HASHTBLSZ_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.HASHTBLSZ */
#define IFX_GETH_MAC_HW_FEATURE1_HASHTBLSZ_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE1_Bits.L3L4FNUM */
#define IFX_GETH_MAC_HW_FEATURE1_L3L4FNUM_LEN (4u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE1_Bits.L3L4FNUM */
#define IFX_GETH_MAC_HW_FEATURE1_L3L4FNUM_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE1_Bits.L3L4FNUM */
#define IFX_GETH_MAC_HW_FEATURE1_L3L4FNUM_OFF (27u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE2_Bits.RXQCNT */
#define IFX_GETH_MAC_HW_FEATURE2_RXQCNT_LEN (4u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE2_Bits.RXQCNT */
#define IFX_GETH_MAC_HW_FEATURE2_RXQCNT_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE2_Bits.RXQCNT */
#define IFX_GETH_MAC_HW_FEATURE2_RXQCNT_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE2_Bits.TXQCNT */
#define IFX_GETH_MAC_HW_FEATURE2_TXQCNT_LEN (4u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE2_Bits.TXQCNT */
#define IFX_GETH_MAC_HW_FEATURE2_TXQCNT_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE2_Bits.TXQCNT */
#define IFX_GETH_MAC_HW_FEATURE2_TXQCNT_OFF (6u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE2_Bits.RXCHCNT */
#define IFX_GETH_MAC_HW_FEATURE2_RXCHCNT_LEN (4u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE2_Bits.RXCHCNT */
#define IFX_GETH_MAC_HW_FEATURE2_RXCHCNT_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE2_Bits.RXCHCNT */
#define IFX_GETH_MAC_HW_FEATURE2_RXCHCNT_OFF (12u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE2_Bits.TXCHCNT */
#define IFX_GETH_MAC_HW_FEATURE2_TXCHCNT_LEN (4u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE2_Bits.TXCHCNT */
#define IFX_GETH_MAC_HW_FEATURE2_TXCHCNT_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE2_Bits.TXCHCNT */
#define IFX_GETH_MAC_HW_FEATURE2_TXCHCNT_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE2_Bits.PPSOUTNUM */
#define IFX_GETH_MAC_HW_FEATURE2_PPSOUTNUM_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE2_Bits.PPSOUTNUM */
#define IFX_GETH_MAC_HW_FEATURE2_PPSOUTNUM_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE2_Bits.PPSOUTNUM */
#define IFX_GETH_MAC_HW_FEATURE2_PPSOUTNUM_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE2_Bits.AUXSNAPNUM */
#define IFX_GETH_MAC_HW_FEATURE2_AUXSNAPNUM_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE2_Bits.AUXSNAPNUM */
#define IFX_GETH_MAC_HW_FEATURE2_AUXSNAPNUM_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE2_Bits.AUXSNAPNUM */
#define IFX_GETH_MAC_HW_FEATURE2_AUXSNAPNUM_OFF (28u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE3_Bits.NRVF */
#define IFX_GETH_MAC_HW_FEATURE3_NRVF_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE3_Bits.NRVF */
#define IFX_GETH_MAC_HW_FEATURE3_NRVF_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE3_Bits.NRVF */
#define IFX_GETH_MAC_HW_FEATURE3_NRVF_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE3_Bits.CBTISEL */
#define IFX_GETH_MAC_HW_FEATURE3_CBTISEL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE3_Bits.CBTISEL */
#define IFX_GETH_MAC_HW_FEATURE3_CBTISEL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE3_Bits.CBTISEL */
#define IFX_GETH_MAC_HW_FEATURE3_CBTISEL_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_HW_FEATURE3_Bits.DVLAN */
#define IFX_GETH_MAC_HW_FEATURE3_DVLAN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_HW_FEATURE3_Bits.DVLAN */
#define IFX_GETH_MAC_HW_FEATURE3_DVLAN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_HW_FEATURE3_Bits.DVLAN */
#define IFX_GETH_MAC_HW_FEATURE3_DVLAN_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.GB */
#define IFX_GETH_MAC_MDIO_ADDRESS_GB_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.GB */
#define IFX_GETH_MAC_MDIO_ADDRESS_GB_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.GB */
#define IFX_GETH_MAC_MDIO_ADDRESS_GB_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.C45E */
#define IFX_GETH_MAC_MDIO_ADDRESS_C45E_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.C45E */
#define IFX_GETH_MAC_MDIO_ADDRESS_C45E_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.C45E */
#define IFX_GETH_MAC_MDIO_ADDRESS_C45E_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.GOC_0 */
#define IFX_GETH_MAC_MDIO_ADDRESS_GOC_0_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.GOC_0 */
#define IFX_GETH_MAC_MDIO_ADDRESS_GOC_0_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.GOC_0 */
#define IFX_GETH_MAC_MDIO_ADDRESS_GOC_0_OFF (2u)

/** \brief Length for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.GOC_1 */
#define IFX_GETH_MAC_MDIO_ADDRESS_GOC_1_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.GOC_1 */
#define IFX_GETH_MAC_MDIO_ADDRESS_GOC_1_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.GOC_1 */
#define IFX_GETH_MAC_MDIO_ADDRESS_GOC_1_OFF (3u)

/** \brief Length for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.SKAP */
#define IFX_GETH_MAC_MDIO_ADDRESS_SKAP_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.SKAP */
#define IFX_GETH_MAC_MDIO_ADDRESS_SKAP_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.SKAP */
#define IFX_GETH_MAC_MDIO_ADDRESS_SKAP_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.CR */
#define IFX_GETH_MAC_MDIO_ADDRESS_CR_LEN (4u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.CR */
#define IFX_GETH_MAC_MDIO_ADDRESS_CR_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.CR */
#define IFX_GETH_MAC_MDIO_ADDRESS_CR_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.NTC */
#define IFX_GETH_MAC_MDIO_ADDRESS_NTC_LEN (3u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.NTC */
#define IFX_GETH_MAC_MDIO_ADDRESS_NTC_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.NTC */
#define IFX_GETH_MAC_MDIO_ADDRESS_NTC_OFF (12u)

/** \brief Length for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.RDA */
#define IFX_GETH_MAC_MDIO_ADDRESS_RDA_LEN (5u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.RDA */
#define IFX_GETH_MAC_MDIO_ADDRESS_RDA_MSK (0x1fu)

/** \brief Offset for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.RDA */
#define IFX_GETH_MAC_MDIO_ADDRESS_RDA_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.PA */
#define IFX_GETH_MAC_MDIO_ADDRESS_PA_LEN (5u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.PA */
#define IFX_GETH_MAC_MDIO_ADDRESS_PA_MSK (0x1fu)

/** \brief Offset for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.PA */
#define IFX_GETH_MAC_MDIO_ADDRESS_PA_OFF (21u)

/** \brief Length for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.BTB */
#define IFX_GETH_MAC_MDIO_ADDRESS_BTB_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.BTB */
#define IFX_GETH_MAC_MDIO_ADDRESS_BTB_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.BTB */
#define IFX_GETH_MAC_MDIO_ADDRESS_BTB_OFF (26u)

/** \brief Length for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.PSE */
#define IFX_GETH_MAC_MDIO_ADDRESS_PSE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.PSE */
#define IFX_GETH_MAC_MDIO_ADDRESS_PSE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_MDIO_ADDRESS_Bits.PSE */
#define IFX_GETH_MAC_MDIO_ADDRESS_PSE_OFF (27u)

/** \brief Length for Ifx_GETH_MAC_MDIO_DATA_Bits.GD */
#define IFX_GETH_MAC_MDIO_DATA_GD_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_DATA_Bits.GD */
#define IFX_GETH_MAC_MDIO_DATA_GD_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_MDIO_DATA_Bits.GD */
#define IFX_GETH_MAC_MDIO_DATA_GD_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_MDIO_DATA_Bits.RA */
#define IFX_GETH_MAC_MDIO_DATA_RA_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_MDIO_DATA_Bits.RA */
#define IFX_GETH_MAC_MDIO_DATA_RA_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_MDIO_DATA_Bits.RA */
#define IFX_GETH_MAC_MDIO_DATA_RA_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_CSR_SW_CTRL_Bits.RCWE */
#define IFX_GETH_MAC_CSR_SW_CTRL_RCWE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CSR_SW_CTRL_Bits.RCWE */
#define IFX_GETH_MAC_CSR_SW_CTRL_RCWE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CSR_SW_CTRL_Bits.RCWE */
#define IFX_GETH_MAC_CSR_SW_CTRL_RCWE_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_CSR_SW_CTRL_Bits.SEEN */
#define IFX_GETH_MAC_CSR_SW_CTRL_SEEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_CSR_SW_CTRL_Bits.SEEN */
#define IFX_GETH_MAC_CSR_SW_CTRL_SEEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_CSR_SW_CTRL_Bits.SEEN */
#define IFX_GETH_MAC_CSR_SW_CTRL_SEEN_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_EXT_CFG1_Bits.SPLOFST */
#define IFX_GETH_MAC_EXT_CFG1_SPLOFST_LEN (7u)

/** \brief Mask for Ifx_GETH_MAC_EXT_CFG1_Bits.SPLOFST */
#define IFX_GETH_MAC_EXT_CFG1_SPLOFST_MSK (0x7fu)

/** \brief Offset for Ifx_GETH_MAC_EXT_CFG1_Bits.SPLOFST */
#define IFX_GETH_MAC_EXT_CFG1_SPLOFST_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_EXT_CFG1_Bits.SPLM */
#define IFX_GETH_MAC_EXT_CFG1_SPLM_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_EXT_CFG1_Bits.SPLM */
#define IFX_GETH_MAC_EXT_CFG1_SPLM_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_EXT_CFG1_Bits.SPLM */
#define IFX_GETH_MAC_EXT_CFG1_SPLM_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_ADDRESS_HIGH0_Bits.ADDRHI */
#define IFX_GETH_MAC_ADDRESS_HIGH0_ADDRHI_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_ADDRESS_HIGH0_Bits.ADDRHI */
#define IFX_GETH_MAC_ADDRESS_HIGH0_ADDRHI_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_ADDRESS_HIGH0_Bits.ADDRHI */
#define IFX_GETH_MAC_ADDRESS_HIGH0_ADDRHI_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_ADDRESS_HIGH0_Bits.DCS */
#define IFX_GETH_MAC_ADDRESS_HIGH0_DCS_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_ADDRESS_HIGH0_Bits.DCS */
#define IFX_GETH_MAC_ADDRESS_HIGH0_DCS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_ADDRESS_HIGH0_Bits.DCS */
#define IFX_GETH_MAC_ADDRESS_HIGH0_DCS_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_ADDRESS_HIGH0_Bits.AE */
#define IFX_GETH_MAC_ADDRESS_HIGH0_AE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_ADDRESS_HIGH0_Bits.AE */
#define IFX_GETH_MAC_ADDRESS_HIGH0_AE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_ADDRESS_HIGH0_Bits.AE */
#define IFX_GETH_MAC_ADDRESS_HIGH0_AE_OFF (31u)

/** \brief Length for Ifx_GETH_MAC_ADDRESS_LOW0_Bits.ADDRLO */
#define IFX_GETH_MAC_ADDRESS_LOW0_ADDRLO_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_ADDRESS_LOW0_Bits.ADDRLO */
#define IFX_GETH_MAC_ADDRESS_LOW0_ADDRLO_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_ADDRESS_LOW0_Bits.ADDRLO */
#define IFX_GETH_MAC_ADDRESS_LOW0_ADDRLO_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.ADDRHI */
#define IFX_GETH_MAC_ADDRESS_HIGH_ADDRHI_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.ADDRHI */
#define IFX_GETH_MAC_ADDRESS_HIGH_ADDRHI_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.ADDRHI */
#define IFX_GETH_MAC_ADDRESS_HIGH_ADDRHI_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.DCS */
#define IFX_GETH_MAC_ADDRESS_HIGH_DCS_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.DCS */
#define IFX_GETH_MAC_ADDRESS_HIGH_DCS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.DCS */
#define IFX_GETH_MAC_ADDRESS_HIGH_DCS_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.MBC */
#define IFX_GETH_MAC_ADDRESS_HIGH_MBC_LEN (6u)

/** \brief Mask for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.MBC */
#define IFX_GETH_MAC_ADDRESS_HIGH_MBC_MSK (0x3fu)

/** \brief Offset for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.MBC */
#define IFX_GETH_MAC_ADDRESS_HIGH_MBC_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.SA */
#define IFX_GETH_MAC_ADDRESS_HIGH_SA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.SA */
#define IFX_GETH_MAC_ADDRESS_HIGH_SA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.SA */
#define IFX_GETH_MAC_ADDRESS_HIGH_SA_OFF (30u)

/** \brief Length for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.AE */
#define IFX_GETH_MAC_ADDRESS_HIGH_AE_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.AE */
#define IFX_GETH_MAC_ADDRESS_HIGH_AE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_ADDRESS_HIGH_Bits.AE */
#define IFX_GETH_MAC_ADDRESS_HIGH_AE_OFF (31u)

/** \brief Length for Ifx_GETH_MAC_ADDRESS_LOW_Bits.ADDRLO */
#define IFX_GETH_MAC_ADDRESS_LOW_ADDRLO_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_ADDRESS_LOW_Bits.ADDRLO */
#define IFX_GETH_MAC_ADDRESS_LOW_ADDRLO_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_ADDRESS_LOW_Bits.ADDRLO */
#define IFX_GETH_MAC_ADDRESS_LOW_ADDRLO_OFF (0u)

/** \brief Length for Ifx_GETH_MMC_CONTROL_Bits.CNTRST */
#define IFX_GETH_MMC_CONTROL_CNTRST_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_CONTROL_Bits.CNTRST */
#define IFX_GETH_MMC_CONTROL_CNTRST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_CONTROL_Bits.CNTRST */
#define IFX_GETH_MMC_CONTROL_CNTRST_OFF (0u)

/** \brief Length for Ifx_GETH_MMC_CONTROL_Bits.CNTSTOPRO */
#define IFX_GETH_MMC_CONTROL_CNTSTOPRO_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_CONTROL_Bits.CNTSTOPRO */
#define IFX_GETH_MMC_CONTROL_CNTSTOPRO_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_CONTROL_Bits.CNTSTOPRO */
#define IFX_GETH_MMC_CONTROL_CNTSTOPRO_OFF (1u)

/** \brief Length for Ifx_GETH_MMC_CONTROL_Bits.RSTONRD */
#define IFX_GETH_MMC_CONTROL_RSTONRD_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_CONTROL_Bits.RSTONRD */
#define IFX_GETH_MMC_CONTROL_RSTONRD_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_CONTROL_Bits.RSTONRD */
#define IFX_GETH_MMC_CONTROL_RSTONRD_OFF (2u)

/** \brief Length for Ifx_GETH_MMC_CONTROL_Bits.CNTFREEZ */
#define IFX_GETH_MMC_CONTROL_CNTFREEZ_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_CONTROL_Bits.CNTFREEZ */
#define IFX_GETH_MMC_CONTROL_CNTFREEZ_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_CONTROL_Bits.CNTFREEZ */
#define IFX_GETH_MMC_CONTROL_CNTFREEZ_OFF (3u)

/** \brief Length for Ifx_GETH_MMC_CONTROL_Bits.CNTPRST */
#define IFX_GETH_MMC_CONTROL_CNTPRST_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_CONTROL_Bits.CNTPRST */
#define IFX_GETH_MMC_CONTROL_CNTPRST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_CONTROL_Bits.CNTPRST */
#define IFX_GETH_MMC_CONTROL_CNTPRST_OFF (4u)

/** \brief Length for Ifx_GETH_MMC_CONTROL_Bits.CNTPRSTLVL */
#define IFX_GETH_MMC_CONTROL_CNTPRSTLVL_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_CONTROL_Bits.CNTPRSTLVL */
#define IFX_GETH_MMC_CONTROL_CNTPRSTLVL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_CONTROL_Bits.CNTPRSTLVL */
#define IFX_GETH_MMC_CONTROL_CNTPRSTLVL_OFF (5u)

/** \brief Length for Ifx_GETH_MMC_CONTROL_Bits.UCDBC */
#define IFX_GETH_MMC_CONTROL_UCDBC_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_CONTROL_Bits.UCDBC */
#define IFX_GETH_MMC_CONTROL_UCDBC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_CONTROL_Bits.UCDBC */
#define IFX_GETH_MMC_CONTROL_UCDBC_OFF (8u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXGBPKTIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXGBPKTIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXGBPKTIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXGBPKTIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXGBPKTIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXGBPKTIS_OFF (0u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXGBOCTIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXGBOCTIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXGBOCTIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXGBOCTIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXGBOCTIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXGBOCTIS_OFF (1u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXGOCTIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXGOCTIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXGOCTIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXGOCTIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXGOCTIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXGOCTIS_OFF (2u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXBCGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXBCGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXBCGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXBCGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXBCGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXBCGPIS_OFF (3u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXMCGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXMCGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXMCGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXMCGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXMCGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXMCGPIS_OFF (4u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXCRCERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXCRCERPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXCRCERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXCRCERPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXCRCERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXCRCERPIS_OFF (5u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXALGNERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXALGNERPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXALGNERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXALGNERPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXALGNERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXALGNERPIS_OFF (6u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXRUNTPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXRUNTPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXRUNTPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXRUNTPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXRUNTPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXRUNTPIS_OFF (7u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXJABERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXJABERPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXJABERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXJABERPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXJABERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXJABERPIS_OFF (8u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXUSIZEGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXUSIZEGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXUSIZEGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXUSIZEGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXUSIZEGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXUSIZEGPIS_OFF (9u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXOSIZEGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXOSIZEGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXOSIZEGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXOSIZEGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXOSIZEGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXOSIZEGPIS_OFF (10u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX64OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX64OCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX64OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX64OCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX64OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX64OCTGBPIS_OFF (11u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX65T127OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX65T127OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX65T127OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_OFF (12u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX128T255OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX128T255OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX128T255OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_OFF (13u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX256T511OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX256T511OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX256T511OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_OFF (14u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX512T1023OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX512T1023OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX512T1023OCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_OFF (15u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX1024TMAXOCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX1024TMAXOCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RX1024TMAXOCTGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_OFF (16u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXUCGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXUCGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXUCGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXUCGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXUCGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXUCGPIS_OFF (17u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXLENERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXLENERPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXLENERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXLENERPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXLENERPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXLENERPIS_OFF (18u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXORANGEPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXORANGEPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXORANGEPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXORANGEPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXORANGEPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXORANGEPIS_OFF (19u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXPAUSPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXPAUSPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXPAUSPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXPAUSPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXPAUSPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXPAUSPIS_OFF (20u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXFOVPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXFOVPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXFOVPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXFOVPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXFOVPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXFOVPIS_OFF (21u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXVLANGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXVLANGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXVLANGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXVLANGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXVLANGBPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXVLANGBPIS_OFF (22u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXWDOGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXWDOGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXWDOGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXWDOGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXWDOGPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXWDOGPIS_OFF (23u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXRCVERRPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXRCVERRPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXRCVERRPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXRCVERRPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXRCVERRPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXRCVERRPIS_OFF (24u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXCTRLPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXCTRLPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXCTRLPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXCTRLPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXCTRLPIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXCTRLPIS_OFF (25u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXLPIUSCIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXLPIUSCIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXLPIUSCIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXLPIUSCIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXLPIUSCIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXLPIUSCIS_OFF (26u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXLPITRCIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXLPITRCIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXLPITRCIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXLPITRCIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_Bits.RXLPITRCIS */
#define IFX_GETH_MMC_RX_INTERRUPT_RXLPITRCIS_OFF (27u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGBOCTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGBOCTIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGBOCTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGBOCTIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGBOCTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGBOCTIS_OFF (0u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGBPKTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGBPKTIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGBPKTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGBPKTIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGBPKTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGBPKTIS_OFF (1u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXBCGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXBCGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXBCGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXBCGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXBCGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXBCGPIS_OFF (2u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXMCGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXMCGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXMCGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXMCGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXMCGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXMCGPIS_OFF (3u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX64OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX64OCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX64OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX64OCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX64OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX64OCTGBPIS_OFF (4u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX65T127OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX65T127OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX65T127OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_OFF (5u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX128T255OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX128T255OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX128T255OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_OFF (6u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX256T511OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX256T511OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX256T511OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_OFF (7u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX512T1023OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX512T1023OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX512T1023OCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_OFF (8u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX1024TMAXOCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX1024TMAXOCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TX1024TMAXOCTGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_OFF (9u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXUCGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXUCGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXUCGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXUCGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXUCGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXUCGBPIS_OFF (10u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXMCGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXMCGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXMCGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXMCGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXMCGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXMCGBPIS_OFF (11u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXBCGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXBCGBPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXBCGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXBCGBPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXBCGBPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXBCGBPIS_OFF (12u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXUFLOWERPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXUFLOWERPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXUFLOWERPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXUFLOWERPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXUFLOWERPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXUFLOWERPIS_OFF (13u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXSCOLGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXSCOLGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXSCOLGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXSCOLGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXSCOLGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXSCOLGPIS_OFF (14u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXMCOLGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXMCOLGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXMCOLGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXMCOLGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXMCOLGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXMCOLGPIS_OFF (15u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXDEFPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXDEFPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXDEFPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXDEFPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXDEFPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXDEFPIS_OFF (16u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXLATCOLPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXLATCOLPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXLATCOLPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXLATCOLPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXLATCOLPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXLATCOLPIS_OFF (17u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXEXCOLPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXEXCOLPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXEXCOLPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXEXCOLPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXEXCOLPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXEXCOLPIS_OFF (18u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXCARERPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXCARERPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXCARERPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXCARERPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXCARERPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXCARERPIS_OFF (19u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGOCTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGOCTIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGOCTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGOCTIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGOCTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGOCTIS_OFF (20u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGPKTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGPKTIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGPKTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGPKTIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXGPKTIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXGPKTIS_OFF (21u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXEXDEFPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXEXDEFPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXEXDEFPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXEXDEFPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXEXDEFPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXEXDEFPIS_OFF (22u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXPAUSPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXPAUSPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXPAUSPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXPAUSPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXPAUSPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXPAUSPIS_OFF (23u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXVLANGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXVLANGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXVLANGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXVLANGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXVLANGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXVLANGPIS_OFF (24u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXOSIZEGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXOSIZEGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXOSIZEGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXOSIZEGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXOSIZEGPIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXOSIZEGPIS_OFF (25u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXLPIUSCIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXLPIUSCIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXLPIUSCIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXLPIUSCIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXLPIUSCIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXLPIUSCIS_OFF (26u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXLPITRCIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXLPITRCIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXLPITRCIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXLPITRCIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_Bits.TXLPITRCIS */
#define IFX_GETH_MMC_TX_INTERRUPT_TXLPITRCIS_OFF (27u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXGBPKTIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXGBPKTIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXGBPKTIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_OFF (0u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXGBOCTIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXGBOCTIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXGBOCTIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_OFF (1u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXGOCTIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXGOCTIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXGOCTIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXGOCTIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXGOCTIM_OFF (2u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXBCGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXBCGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXBCGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXBCGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXBCGPIM_OFF (3u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXMCGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXMCGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXMCGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXMCGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXMCGPIM_OFF (4u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXCRCERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXCRCERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXCRCERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_OFF (5u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXALGNERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXALGNERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXALGNERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_OFF (6u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXRUNTPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXRUNTPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXRUNTPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_OFF (7u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXJABERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXJABERPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXJABERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXJABERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXJABERPIM_OFF (8u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXUSIZEGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXUSIZEGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXUSIZEGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_OFF (9u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXOSIZEGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXOSIZEGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXOSIZEGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_OFF (10u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX64OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX64OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX64OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_OFF (11u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX65T127OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX65T127OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX65T127OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_OFF (12u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX128T255OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX128T255OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX128T255OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_OFF (13u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX256T511OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX256T511OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX256T511OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_OFF (14u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX512T1023OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX512T1023OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX512T1023OCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_OFF (15u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX1024TMAXOCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX1024TMAXOCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RX1024TMAXOCTGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_OFF (16u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXUCGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXUCGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXUCGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXUCGPIM_OFF (17u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXLENERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXLENERPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXLENERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXLENERPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXLENERPIM_OFF (18u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXORANGEPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXORANGEPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXORANGEPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_OFF (19u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXPAUSPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXPAUSPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXPAUSPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_OFF (20u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXFOVPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXFOVPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXFOVPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXFOVPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXFOVPIM_OFF (21u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXVLANGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXVLANGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXVLANGBPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_OFF (22u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXWDOGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXWDOGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXWDOGPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_OFF (23u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXRCVERRPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXRCVERRPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXRCVERRPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_OFF (24u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXCTRLPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXCTRLPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXCTRLPIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_OFF (25u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXLPIUSCIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXLPIUSCIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXLPIUSCIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_OFF (26u)

/** \brief Length for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXLPITRCIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXLPITRCIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_RX_INTERRUPT_MASK_Bits.RXLPITRCIM */
#define IFX_GETH_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_OFF (27u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGBOCTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGBOCTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGBOCTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_OFF (0u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGBPKTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGBPKTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGBPKTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_OFF (1u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXBCGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXBCGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXBCGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXBCGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXBCGPIM_OFF (2u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXMCGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXMCGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXMCGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXMCGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXMCGPIM_OFF (3u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX64OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX64OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX64OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_OFF (4u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX65T127OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX65T127OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX65T127OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_OFF (5u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX128T255OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX128T255OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX128T255OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_OFF (6u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX256T511OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX256T511OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX256T511OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_OFF (7u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX512T1023OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX512T1023OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX512T1023OCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_OFF (8u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX1024TMAXOCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX1024TMAXOCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TX1024TMAXOCTGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_OFF (9u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXUCGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXUCGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXUCGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_OFF (10u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXMCGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXMCGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXMCGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_OFF (11u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXBCGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXBCGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXBCGBPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_OFF (12u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXUFLOWERPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXUFLOWERPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXUFLOWERPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_OFF (13u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXSCOLGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXSCOLGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXSCOLGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_OFF (14u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXMCOLGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXMCOLGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXMCOLGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_OFF (15u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXDEFPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXDEFPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXDEFPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXDEFPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXDEFPIM_OFF (16u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXLATCOLPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXLATCOLPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXLATCOLPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_OFF (17u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXEXCOLPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXEXCOLPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXEXCOLPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_OFF (18u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXCARERPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXCARERPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXCARERPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXCARERPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXCARERPIM_OFF (19u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGOCTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGOCTIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGOCTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGOCTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGOCTIM_OFF (20u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGPKTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGPKTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXGPKTIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXGPKTIM_OFF (21u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXEXDEFPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXEXDEFPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXEXDEFPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_OFF (22u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXPAUSPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXPAUSPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXPAUSPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_OFF (23u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXVLANGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXVLANGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXVLANGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_OFF (24u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXOSIZEGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXOSIZEGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXOSIZEGPIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_OFF (25u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXLPIUSCIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXLPIUSCIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXLPIUSCIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_OFF (26u)

/** \brief Length for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXLPITRCIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXLPITRCIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_TX_INTERRUPT_MASK_Bits.TXLPITRCIM */
#define IFX_GETH_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_OFF (27u)

/** \brief Length for Ifx_GETH_TX_OCTET_COUNT_GOOD_BAD_Bits.TXOCTGB */
#define IFX_GETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_LEN (32u)

/** \brief Mask for Ifx_GETH_TX_OCTET_COUNT_GOOD_BAD_Bits.TXOCTGB */
#define IFX_GETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_TX_OCTET_COUNT_GOOD_BAD_Bits.TXOCTGB */
#define IFX_GETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_TX_PACKET_COUNT_GOOD_BAD_Bits.TXPKTGB */
#define IFX_GETH_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_PACKET_COUNT_GOOD_BAD_Bits.TXPKTGB */
#define IFX_GETH_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_PACKET_COUNT_GOOD_BAD_Bits.TXPKTGB */
#define IFX_GETH_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_OFF (0u)

/** \brief Length for Ifx_GETH_TX_BROADCAST_PACKETS_GOOD_Bits.TXBCASTG */
#define IFX_GETH_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_BROADCAST_PACKETS_GOOD_Bits.TXBCASTG */
#define IFX_GETH_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_BROADCAST_PACKETS_GOOD_Bits.TXBCASTG */
#define IFX_GETH_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_OFF (0u)

/** \brief Length for Ifx_GETH_TX_MULTICAST_PACKETS_GOOD_Bits.TXMCASTG */
#define IFX_GETH_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_MULTICAST_PACKETS_GOOD_Bits.TXMCASTG */
#define IFX_GETH_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_MULTICAST_PACKETS_GOOD_Bits.TXMCASTG */
#define IFX_GETH_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_OFF (0u)

/** \brief Length for Ifx_GETH_TX_64OCTETS_PACKETS_GOOD_BAD_Bits.TX64OCTGB */
#define IFX_GETH_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_64OCTETS_PACKETS_GOOD_BAD_Bits.TX64OCTGB */
#define IFX_GETH_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_64OCTETS_PACKETS_GOOD_BAD_Bits.TX64OCTGB */
#define IFX_GETH_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_TX_65TO127OCTETS_PACKETS_GOOD_BAD_Bits.TX65_127OCTGB */
#define IFX_GETH_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_65TO127OCTETS_PACKETS_GOOD_BAD_Bits.TX65_127OCTGB */
#define IFX_GETH_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_65TO127OCTETS_PACKETS_GOOD_BAD_Bits.TX65_127OCTGB */
#define IFX_GETH_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_TX_128TO255OCTETS_PACKETS_GOOD_BAD_Bits.TX128_255OCTGB */
#define IFX_GETH_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_128TO255OCTETS_PACKETS_GOOD_BAD_Bits.TX128_255OCTGB */
#define IFX_GETH_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_128TO255OCTETS_PACKETS_GOOD_BAD_Bits.TX128_255OCTGB */
#define IFX_GETH_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_TX_256TO511OCTETS_PACKETS_GOOD_BAD_Bits.TX256_511OCTGB */
#define IFX_GETH_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_256TO511OCTETS_PACKETS_GOOD_BAD_Bits.TX256_511OCTGB */
#define IFX_GETH_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_256TO511OCTETS_PACKETS_GOOD_BAD_Bits.TX256_511OCTGB */
#define IFX_GETH_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_Bits.TX512_1023OCTGB */
#define IFX_GETH_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_Bits.TX512_1023OCTGB */
#define IFX_GETH_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_Bits.TX512_1023OCTGB */
#define IFX_GETH_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_Bits.TX1024_MAXOCTGB */
#define IFX_GETH_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_Bits.TX1024_MAXOCTGB */
#define IFX_GETH_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_Bits.TX1024_MAXOCTGB */
#define IFX_GETH_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_TX_UNICAST_PACKETS_GOOD_BAD_Bits.TXUCASTGB */
#define IFX_GETH_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_UNICAST_PACKETS_GOOD_BAD_Bits.TXUCASTGB */
#define IFX_GETH_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_UNICAST_PACKETS_GOOD_BAD_Bits.TXUCASTGB */
#define IFX_GETH_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_OFF (0u)

/** \brief Length for Ifx_GETH_TX_MULTICAST_PACKETS_GOOD_BAD_Bits.TXMCASTGB */
#define IFX_GETH_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_MULTICAST_PACKETS_GOOD_BAD_Bits.TXMCASTGB */
#define IFX_GETH_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_MULTICAST_PACKETS_GOOD_BAD_Bits.TXMCASTGB */
#define IFX_GETH_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_OFF (0u)

/** \brief Length for Ifx_GETH_TX_BROADCAST_PACKETS_GOOD_BAD_Bits.TXBCASTGB */
#define IFX_GETH_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_BROADCAST_PACKETS_GOOD_BAD_Bits.TXBCASTGB */
#define IFX_GETH_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_BROADCAST_PACKETS_GOOD_BAD_Bits.TXBCASTGB */
#define IFX_GETH_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_OFF (0u)

/** \brief Length for Ifx_GETH_TX_UNDERFLOW_ERROR_PACKETS_Bits.TXUNDRFLW */
#define IFX_GETH_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_UNDERFLOW_ERROR_PACKETS_Bits.TXUNDRFLW */
#define IFX_GETH_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_UNDERFLOW_ERROR_PACKETS_Bits.TXUNDRFLW */
#define IFX_GETH_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_OFF (0u)

/** \brief Length for Ifx_GETH_TX_SINGLE_COLLISION_GOOD_PACKETS_Bits.TXSNGLCOLG */
#define IFX_GETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_SINGLE_COLLISION_GOOD_PACKETS_Bits.TXSNGLCOLG */
#define IFX_GETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_SINGLE_COLLISION_GOOD_PACKETS_Bits.TXSNGLCOLG */
#define IFX_GETH_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_OFF (0u)

/** \brief Length for Ifx_GETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_Bits.TXMULTCOLG */
#define IFX_GETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_Bits.TXMULTCOLG */
#define IFX_GETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_Bits.TXMULTCOLG */
#define IFX_GETH_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_OFF (0u)

/** \brief Length for Ifx_GETH_TX_DEFERRED_PACKETS_Bits.TXDEFRD */
#define IFX_GETH_TX_DEFERRED_PACKETS_TXDEFRD_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_DEFERRED_PACKETS_Bits.TXDEFRD */
#define IFX_GETH_TX_DEFERRED_PACKETS_TXDEFRD_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_DEFERRED_PACKETS_Bits.TXDEFRD */
#define IFX_GETH_TX_DEFERRED_PACKETS_TXDEFRD_OFF (0u)

/** \brief Length for Ifx_GETH_TX_LATE_COLLISION_PACKETS_Bits.TXLATECOL */
#define IFX_GETH_TX_LATE_COLLISION_PACKETS_TXLATECOL_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_LATE_COLLISION_PACKETS_Bits.TXLATECOL */
#define IFX_GETH_TX_LATE_COLLISION_PACKETS_TXLATECOL_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_LATE_COLLISION_PACKETS_Bits.TXLATECOL */
#define IFX_GETH_TX_LATE_COLLISION_PACKETS_TXLATECOL_OFF (0u)

/** \brief Length for Ifx_GETH_TX_EXCESSIVE_COLLISION_PACKETS_Bits.TXEXSCOL */
#define IFX_GETH_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_EXCESSIVE_COLLISION_PACKETS_Bits.TXEXSCOL */
#define IFX_GETH_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_EXCESSIVE_COLLISION_PACKETS_Bits.TXEXSCOL */
#define IFX_GETH_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_OFF (0u)

/** \brief Length for Ifx_GETH_TX_CARRIER_ERROR_PACKETS_Bits.TXCARR */
#define IFX_GETH_TX_CARRIER_ERROR_PACKETS_TXCARR_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_CARRIER_ERROR_PACKETS_Bits.TXCARR */
#define IFX_GETH_TX_CARRIER_ERROR_PACKETS_TXCARR_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_CARRIER_ERROR_PACKETS_Bits.TXCARR */
#define IFX_GETH_TX_CARRIER_ERROR_PACKETS_TXCARR_OFF (0u)

/** \brief Length for Ifx_GETH_TX_OCTET_COUNT_GOOD_Bits.TXOCTG */
#define IFX_GETH_TX_OCTET_COUNT_GOOD_TXOCTG_LEN (32u)

/** \brief Mask for Ifx_GETH_TX_OCTET_COUNT_GOOD_Bits.TXOCTG */
#define IFX_GETH_TX_OCTET_COUNT_GOOD_TXOCTG_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_TX_OCTET_COUNT_GOOD_Bits.TXOCTG */
#define IFX_GETH_TX_OCTET_COUNT_GOOD_TXOCTG_OFF (0u)

/** \brief Length for Ifx_GETH_TX_PACKET_COUNT_GOOD_Bits.TXPKTG */
#define IFX_GETH_TX_PACKET_COUNT_GOOD_TXPKTG_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_PACKET_COUNT_GOOD_Bits.TXPKTG */
#define IFX_GETH_TX_PACKET_COUNT_GOOD_TXPKTG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_PACKET_COUNT_GOOD_Bits.TXPKTG */
#define IFX_GETH_TX_PACKET_COUNT_GOOD_TXPKTG_OFF (0u)

/** \brief Length for Ifx_GETH_TX_EXCESSIVE_DEFERRAL_ERROR_Bits.TXEXSDEF */
#define IFX_GETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_EXCESSIVE_DEFERRAL_ERROR_Bits.TXEXSDEF */
#define IFX_GETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_EXCESSIVE_DEFERRAL_ERROR_Bits.TXEXSDEF */
#define IFX_GETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_OFF (0u)

/** \brief Length for Ifx_GETH_TX_PAUSE_PACKETS_Bits.TXPAUSE */
#define IFX_GETH_TX_PAUSE_PACKETS_TXPAUSE_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_PAUSE_PACKETS_Bits.TXPAUSE */
#define IFX_GETH_TX_PAUSE_PACKETS_TXPAUSE_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_PAUSE_PACKETS_Bits.TXPAUSE */
#define IFX_GETH_TX_PAUSE_PACKETS_TXPAUSE_OFF (0u)

/** \brief Length for Ifx_GETH_TX_VLAN_PACKETS_GOOD_Bits.TXVLANG */
#define IFX_GETH_TX_VLAN_PACKETS_GOOD_TXVLANG_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_VLAN_PACKETS_GOOD_Bits.TXVLANG */
#define IFX_GETH_TX_VLAN_PACKETS_GOOD_TXVLANG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_VLAN_PACKETS_GOOD_Bits.TXVLANG */
#define IFX_GETH_TX_VLAN_PACKETS_GOOD_TXVLANG_OFF (0u)

/** \brief Length for Ifx_GETH_TX_OSIZE_PACKETS_GOOD_Bits.TXOSIZG */
#define IFX_GETH_TX_OSIZE_PACKETS_GOOD_TXOSIZG_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_OSIZE_PACKETS_GOOD_Bits.TXOSIZG */
#define IFX_GETH_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_OSIZE_PACKETS_GOOD_Bits.TXOSIZG */
#define IFX_GETH_TX_OSIZE_PACKETS_GOOD_TXOSIZG_OFF (0u)

/** \brief Length for Ifx_GETH_RX_PACKETS_COUNT_GOOD_BAD_Bits.RXPKTGB */
#define IFX_GETH_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_PACKETS_COUNT_GOOD_BAD_Bits.RXPKTGB */
#define IFX_GETH_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_PACKETS_COUNT_GOOD_BAD_Bits.RXPKTGB */
#define IFX_GETH_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_OFF (0u)

/** \brief Length for Ifx_GETH_RX_OCTET_COUNT_GOOD_BAD_Bits.RXOCTGB */
#define IFX_GETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_LEN (32u)

/** \brief Mask for Ifx_GETH_RX_OCTET_COUNT_GOOD_BAD_Bits.RXOCTGB */
#define IFX_GETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RX_OCTET_COUNT_GOOD_BAD_Bits.RXOCTGB */
#define IFX_GETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_RX_OCTET_COUNT_GOOD_Bits.RXOCTG */
#define IFX_GETH_RX_OCTET_COUNT_GOOD_RXOCTG_LEN (32u)

/** \brief Mask for Ifx_GETH_RX_OCTET_COUNT_GOOD_Bits.RXOCTG */
#define IFX_GETH_RX_OCTET_COUNT_GOOD_RXOCTG_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RX_OCTET_COUNT_GOOD_Bits.RXOCTG */
#define IFX_GETH_RX_OCTET_COUNT_GOOD_RXOCTG_OFF (0u)

/** \brief Length for Ifx_GETH_RX_BROADCAST_PACKETS_GOOD_Bits.RXBCASTG */
#define IFX_GETH_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_BROADCAST_PACKETS_GOOD_Bits.RXBCASTG */
#define IFX_GETH_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_BROADCAST_PACKETS_GOOD_Bits.RXBCASTG */
#define IFX_GETH_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_OFF (0u)

/** \brief Length for Ifx_GETH_RX_MULTICAST_PACKETS_GOOD_Bits.RXMCASTG */
#define IFX_GETH_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_MULTICAST_PACKETS_GOOD_Bits.RXMCASTG */
#define IFX_GETH_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_MULTICAST_PACKETS_GOOD_Bits.RXMCASTG */
#define IFX_GETH_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_OFF (0u)

/** \brief Length for Ifx_GETH_RX_CRC_ERROR_PACKETS_Bits.RXCRCERR */
#define IFX_GETH_RX_CRC_ERROR_PACKETS_RXCRCERR_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_CRC_ERROR_PACKETS_Bits.RXCRCERR */
#define IFX_GETH_RX_CRC_ERROR_PACKETS_RXCRCERR_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_CRC_ERROR_PACKETS_Bits.RXCRCERR */
#define IFX_GETH_RX_CRC_ERROR_PACKETS_RXCRCERR_OFF (0u)

/** \brief Length for Ifx_GETH_RX_ALIGNMENT_ERROR_PACKETS_Bits.RXALGNERR */
#define IFX_GETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_ALIGNMENT_ERROR_PACKETS_Bits.RXALGNERR */
#define IFX_GETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_ALIGNMENT_ERROR_PACKETS_Bits.RXALGNERR */
#define IFX_GETH_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_OFF (0u)

/** \brief Length for Ifx_GETH_RX_RUNT_ERROR_PACKETS_Bits.RXRUNTERR */
#define IFX_GETH_RX_RUNT_ERROR_PACKETS_RXRUNTERR_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_RUNT_ERROR_PACKETS_Bits.RXRUNTERR */
#define IFX_GETH_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_RUNT_ERROR_PACKETS_Bits.RXRUNTERR */
#define IFX_GETH_RX_RUNT_ERROR_PACKETS_RXRUNTERR_OFF (0u)

/** \brief Length for Ifx_GETH_RX_JABBER_ERROR_PACKETS_Bits.RXJABERR */
#define IFX_GETH_RX_JABBER_ERROR_PACKETS_RXJABERR_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_JABBER_ERROR_PACKETS_Bits.RXJABERR */
#define IFX_GETH_RX_JABBER_ERROR_PACKETS_RXJABERR_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_JABBER_ERROR_PACKETS_Bits.RXJABERR */
#define IFX_GETH_RX_JABBER_ERROR_PACKETS_RXJABERR_OFF (0u)

/** \brief Length for Ifx_GETH_RX_UNDERSIZE_PACKETS_GOOD_Bits.RXUNDERSZG */
#define IFX_GETH_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_UNDERSIZE_PACKETS_GOOD_Bits.RXUNDERSZG */
#define IFX_GETH_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_UNDERSIZE_PACKETS_GOOD_Bits.RXUNDERSZG */
#define IFX_GETH_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_OFF (0u)

/** \brief Length for Ifx_GETH_RX_OVERSIZE_PACKETS_GOOD_Bits.RXOVERSZG */
#define IFX_GETH_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_OVERSIZE_PACKETS_GOOD_Bits.RXOVERSZG */
#define IFX_GETH_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_OVERSIZE_PACKETS_GOOD_Bits.RXOVERSZG */
#define IFX_GETH_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_OFF (0u)

/** \brief Length for Ifx_GETH_RX_64OCTETS_PACKETS_GOOD_BAD_Bits.RX64OCTGB */
#define IFX_GETH_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_64OCTETS_PACKETS_GOOD_BAD_Bits.RX64OCTGB */
#define IFX_GETH_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_64OCTETS_PACKETS_GOOD_BAD_Bits.RX64OCTGB */
#define IFX_GETH_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_RX_65TO127OCTETS_PACKETS_GOOD_BAD_Bits.RX65_127OCTGB */
#define IFX_GETH_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_65TO127OCTETS_PACKETS_GOOD_BAD_Bits.RX65_127OCTGB */
#define IFX_GETH_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_65TO127OCTETS_PACKETS_GOOD_BAD_Bits.RX65_127OCTGB */
#define IFX_GETH_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_RX_128TO255OCTETS_PACKETS_GOOD_BAD_Bits.RX128_255OCTGB */
#define IFX_GETH_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_128TO255OCTETS_PACKETS_GOOD_BAD_Bits.RX128_255OCTGB */
#define IFX_GETH_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_128TO255OCTETS_PACKETS_GOOD_BAD_Bits.RX128_255OCTGB */
#define IFX_GETH_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_RX_256TO511OCTETS_PACKETS_GOOD_BAD_Bits.RX256_511OCTGB */
#define IFX_GETH_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_256TO511OCTETS_PACKETS_GOOD_BAD_Bits.RX256_511OCTGB */
#define IFX_GETH_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_256TO511OCTETS_PACKETS_GOOD_BAD_Bits.RX256_511OCTGB */
#define IFX_GETH_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_Bits.RX512_1023OCTGB */
#define IFX_GETH_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_Bits.RX512_1023OCTGB */
#define IFX_GETH_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_Bits.RX512_1023OCTGB */
#define IFX_GETH_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_Bits.RX1024_MAXOCTGB */
#define IFX_GETH_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_Bits.RX1024_MAXOCTGB */
#define IFX_GETH_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_Bits.RX1024_MAXOCTGB */
#define IFX_GETH_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_OFF (0u)

/** \brief Length for Ifx_GETH_RX_UNICAST_PACKETS_GOOD_Bits.RXUCASTG */
#define IFX_GETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_UNICAST_PACKETS_GOOD_Bits.RXUCASTG */
#define IFX_GETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_UNICAST_PACKETS_GOOD_Bits.RXUCASTG */
#define IFX_GETH_RX_UNICAST_PACKETS_GOOD_RXUCASTG_OFF (0u)

/** \brief Length for Ifx_GETH_RX_LENGTH_ERROR_PACKETS_Bits.RXLENERR */
#define IFX_GETH_RX_LENGTH_ERROR_PACKETS_RXLENERR_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_LENGTH_ERROR_PACKETS_Bits.RXLENERR */
#define IFX_GETH_RX_LENGTH_ERROR_PACKETS_RXLENERR_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_LENGTH_ERROR_PACKETS_Bits.RXLENERR */
#define IFX_GETH_RX_LENGTH_ERROR_PACKETS_RXLENERR_OFF (0u)

/** \brief Length for Ifx_GETH_RX_OUT_OF_RANGE_TYPE_PACKETS_Bits.RXOUTOFRNG */
#define IFX_GETH_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_OUT_OF_RANGE_TYPE_PACKETS_Bits.RXOUTOFRNG */
#define IFX_GETH_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_OUT_OF_RANGE_TYPE_PACKETS_Bits.RXOUTOFRNG */
#define IFX_GETH_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_OFF (0u)

/** \brief Length for Ifx_GETH_RX_PAUSE_PACKETS_Bits.RXPAUSEPKT */
#define IFX_GETH_RX_PAUSE_PACKETS_RXPAUSEPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_PAUSE_PACKETS_Bits.RXPAUSEPKT */
#define IFX_GETH_RX_PAUSE_PACKETS_RXPAUSEPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_PAUSE_PACKETS_Bits.RXPAUSEPKT */
#define IFX_GETH_RX_PAUSE_PACKETS_RXPAUSEPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RX_FIFO_OVERFLOW_PACKETS_Bits.RXFIFOOVFL */
#define IFX_GETH_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_FIFO_OVERFLOW_PACKETS_Bits.RXFIFOOVFL */
#define IFX_GETH_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_FIFO_OVERFLOW_PACKETS_Bits.RXFIFOOVFL */
#define IFX_GETH_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_OFF (0u)

/** \brief Length for Ifx_GETH_RX_VLAN_PACKETS_GOOD_BAD_Bits.RXVLANPKTGB */
#define IFX_GETH_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_VLAN_PACKETS_GOOD_BAD_Bits.RXVLANPKTGB */
#define IFX_GETH_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_VLAN_PACKETS_GOOD_BAD_Bits.RXVLANPKTGB */
#define IFX_GETH_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_OFF (0u)

/** \brief Length for Ifx_GETH_RX_WATCHDOG_ERROR_PACKETS_Bits.RXWDGERR */
#define IFX_GETH_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_WATCHDOG_ERROR_PACKETS_Bits.RXWDGERR */
#define IFX_GETH_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_WATCHDOG_ERROR_PACKETS_Bits.RXWDGERR */
#define IFX_GETH_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_OFF (0u)

/** \brief Length for Ifx_GETH_RX_RECEIVE_ERROR_PACKETS_Bits.RXRCVERR */
#define IFX_GETH_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_RECEIVE_ERROR_PACKETS_Bits.RXRCVERR */
#define IFX_GETH_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_RECEIVE_ERROR_PACKETS_Bits.RXRCVERR */
#define IFX_GETH_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_OFF (0u)

/** \brief Length for Ifx_GETH_RX_CONTROL_PACKETS_GOOD_Bits.RXCTRLG */
#define IFX_GETH_RX_CONTROL_PACKETS_GOOD_RXCTRLG_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_CONTROL_PACKETS_GOOD_Bits.RXCTRLG */
#define IFX_GETH_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_CONTROL_PACKETS_GOOD_Bits.RXCTRLG */
#define IFX_GETH_RX_CONTROL_PACKETS_GOOD_RXCTRLG_OFF (0u)

/** \brief Length for Ifx_GETH_TX_LPI_USEC_CNTR_Bits.TXLPIUSC */
#define IFX_GETH_TX_LPI_USEC_CNTR_TXLPIUSC_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_LPI_USEC_CNTR_Bits.TXLPIUSC */
#define IFX_GETH_TX_LPI_USEC_CNTR_TXLPIUSC_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_LPI_USEC_CNTR_Bits.TXLPIUSC */
#define IFX_GETH_TX_LPI_USEC_CNTR_TXLPIUSC_OFF (0u)

/** \brief Length for Ifx_GETH_TX_LPI_TRAN_CNTR_Bits.TXLPITRC */
#define IFX_GETH_TX_LPI_TRAN_CNTR_TXLPITRC_LEN (16u)

/** \brief Mask for Ifx_GETH_TX_LPI_TRAN_CNTR_Bits.TXLPITRC */
#define IFX_GETH_TX_LPI_TRAN_CNTR_TXLPITRC_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_TX_LPI_TRAN_CNTR_Bits.TXLPITRC */
#define IFX_GETH_TX_LPI_TRAN_CNTR_TXLPITRC_OFF (0u)

/** \brief Length for Ifx_GETH_RX_LPI_USEC_CNTR_Bits.RXLPIUSC */
#define IFX_GETH_RX_LPI_USEC_CNTR_RXLPIUSC_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_LPI_USEC_CNTR_Bits.RXLPIUSC */
#define IFX_GETH_RX_LPI_USEC_CNTR_RXLPIUSC_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_LPI_USEC_CNTR_Bits.RXLPIUSC */
#define IFX_GETH_RX_LPI_USEC_CNTR_RXLPIUSC_OFF (0u)

/** \brief Length for Ifx_GETH_RX_LPI_TRAN_CNTR_Bits.RXLPITRC */
#define IFX_GETH_RX_LPI_TRAN_CNTR_RXLPITRC_LEN (16u)

/** \brief Mask for Ifx_GETH_RX_LPI_TRAN_CNTR_Bits.RXLPITRC */
#define IFX_GETH_RX_LPI_TRAN_CNTR_RXLPITRC_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RX_LPI_TRAN_CNTR_Bits.RXLPITRC */
#define IFX_GETH_RX_LPI_TRAN_CNTR_RXLPITRC_OFF (0u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4GPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4GPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4GPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_OFF (0u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4HERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4HERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4HERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_OFF (1u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4NOPAYPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4NOPAYPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4NOPAYPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_OFF (2u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4FRAGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4FRAGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4FRAGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_OFF (3u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4UDSBLPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4UDSBLPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4UDSBLPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_OFF (4u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6GPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6GPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6GPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_OFF (5u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6HERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6HERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6HERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_OFF (6u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6NOPAYPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6NOPAYPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6NOPAYPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_OFF (7u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_OFF (8u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_OFF (9u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_OFF (10u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_OFF (11u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPGPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_OFF (12u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPERPIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_OFF (13u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4GOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4GOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4GOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_OFF (16u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4HEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4HEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4HEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_OFF (17u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4NOPAYOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4NOPAYOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4NOPAYOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_OFF (18u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4FRAGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4FRAGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4FRAGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_OFF (19u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4UDSBLOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4UDSBLOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV4UDSBLOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_OFF (20u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6GOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6GOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6GOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_OFF (21u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6HEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6HEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6HEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_OFF (22u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6NOPAYOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6NOPAYOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXIPV6NOPAYOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_OFF (23u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_OFF (24u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXUDPEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_OFF (25u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_OFF (26u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXTCPEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_OFF (27u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPGOIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_OFF (28u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_MASK_Bits.RXICMPEROIM */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_OFF (29u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4GPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4GPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4GPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_OFF (0u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4HERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4HERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4HERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_OFF (1u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4NOPAYPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4NOPAYPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4NOPAYPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_OFF (2u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4FRAGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4FRAGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4FRAGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_OFF (3u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4UDSBLPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4UDSBLPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4UDSBLPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_OFF (4u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6GPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6GPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6GPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_OFF (5u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6HERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6HERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6HERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_OFF (6u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6NOPAYPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6NOPAYPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6NOPAYPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_OFF (7u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_OFF (8u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_OFF (9u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_OFF (10u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_OFF (11u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPGPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_OFF (12u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPERPIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_OFF (13u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4GOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4GOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4GOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_OFF (16u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4HEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4HEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4HEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_OFF (17u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4NOPAYOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4NOPAYOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4NOPAYOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_OFF (18u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4FRAGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4FRAGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4FRAGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_OFF (19u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4UDSBLOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4UDSBLOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV4UDSBLOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_OFF (20u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6GOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6GOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6GOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_OFF (21u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6HEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6HEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6HEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_OFF (22u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6NOPAYOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6NOPAYOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXIPV6NOPAYOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_OFF (23u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_OFF (24u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXUDPEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_OFF (25u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_OFF (26u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXTCPEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_OFF (27u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPGOIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_OFF (28u)

/** \brief Length for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MMC_IPC_RX_INTERRUPT_Bits.RXICMPEROIS */
#define IFX_GETH_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_OFF (29u)

/** \brief Length for Ifx_GETH_RXIPV4_GOOD_PACKETS_Bits.RXIPV4GDPKT */
#define IFX_GETH_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXIPV4_GOOD_PACKETS_Bits.RXIPV4GDPKT */
#define IFX_GETH_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXIPV4_GOOD_PACKETS_Bits.RXIPV4GDPKT */
#define IFX_GETH_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV4_HEADER_ERROR_PACKETS_Bits.RXIPV4HDRERRPKT */
#define IFX_GETH_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXIPV4_HEADER_ERROR_PACKETS_Bits.RXIPV4HDRERRPKT */
#define IFX_GETH_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXIPV4_HEADER_ERROR_PACKETS_Bits.RXIPV4HDRERRPKT */
#define IFX_GETH_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV4_NO_PAYLOAD_PACKETS_Bits.RXIPV4NOPAYPKT */
#define IFX_GETH_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXIPV4_NO_PAYLOAD_PACKETS_Bits.RXIPV4NOPAYPKT */
#define IFX_GETH_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXIPV4_NO_PAYLOAD_PACKETS_Bits.RXIPV4NOPAYPKT */
#define IFX_GETH_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV4_FRAGMENTED_PACKETS_Bits.RXIPV4FRAGPKT */
#define IFX_GETH_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXIPV4_FRAGMENTED_PACKETS_Bits.RXIPV4FRAGPKT */
#define IFX_GETH_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXIPV4_FRAGMENTED_PACKETS_Bits.RXIPV4FRAGPKT */
#define IFX_GETH_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_Bits.RXIPV4UDSBLPKT */
#define IFX_GETH_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_Bits.RXIPV4UDSBLPKT */
#define IFX_GETH_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_Bits.RXIPV4UDSBLPKT */
#define IFX_GETH_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV6_GOOD_PACKETS_Bits.RXIPV6GDPKT */
#define IFX_GETH_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXIPV6_GOOD_PACKETS_Bits.RXIPV6GDPKT */
#define IFX_GETH_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXIPV6_GOOD_PACKETS_Bits.RXIPV6GDPKT */
#define IFX_GETH_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV6_HEADER_ERROR_PACKETS_Bits.RXIPV6HDRERRPKT */
#define IFX_GETH_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXIPV6_HEADER_ERROR_PACKETS_Bits.RXIPV6HDRERRPKT */
#define IFX_GETH_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXIPV6_HEADER_ERROR_PACKETS_Bits.RXIPV6HDRERRPKT */
#define IFX_GETH_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV6_NO_PAYLOAD_PACKETS_Bits.RXIPV6NOPAYPKT */
#define IFX_GETH_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXIPV6_NO_PAYLOAD_PACKETS_Bits.RXIPV6NOPAYPKT */
#define IFX_GETH_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXIPV6_NO_PAYLOAD_PACKETS_Bits.RXIPV6NOPAYPKT */
#define IFX_GETH_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXUDP_GOOD_PACKETS_Bits.RXUDPGDPKT */
#define IFX_GETH_RXUDP_GOOD_PACKETS_RXUDPGDPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXUDP_GOOD_PACKETS_Bits.RXUDPGDPKT */
#define IFX_GETH_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXUDP_GOOD_PACKETS_Bits.RXUDPGDPKT */
#define IFX_GETH_RXUDP_GOOD_PACKETS_RXUDPGDPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXUDP_ERROR_PACKETS_Bits.RXUDPERRPKT */
#define IFX_GETH_RXUDP_ERROR_PACKETS_RXUDPERRPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXUDP_ERROR_PACKETS_Bits.RXUDPERRPKT */
#define IFX_GETH_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXUDP_ERROR_PACKETS_Bits.RXUDPERRPKT */
#define IFX_GETH_RXUDP_ERROR_PACKETS_RXUDPERRPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXTCP_GOOD_PACKETS_Bits.RXTCPGDPKT */
#define IFX_GETH_RXTCP_GOOD_PACKETS_RXTCPGDPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXTCP_GOOD_PACKETS_Bits.RXTCPGDPKT */
#define IFX_GETH_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXTCP_GOOD_PACKETS_Bits.RXTCPGDPKT */
#define IFX_GETH_RXTCP_GOOD_PACKETS_RXTCPGDPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXTCP_ERROR_PACKETS_Bits.RXTCPERRPKT */
#define IFX_GETH_RXTCP_ERROR_PACKETS_RXTCPERRPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXTCP_ERROR_PACKETS_Bits.RXTCPERRPKT */
#define IFX_GETH_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXTCP_ERROR_PACKETS_Bits.RXTCPERRPKT */
#define IFX_GETH_RXTCP_ERROR_PACKETS_RXTCPERRPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXICMP_GOOD_PACKETS_Bits.RXICMPGDPKT */
#define IFX_GETH_RXICMP_GOOD_PACKETS_RXICMPGDPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXICMP_GOOD_PACKETS_Bits.RXICMPGDPKT */
#define IFX_GETH_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXICMP_GOOD_PACKETS_Bits.RXICMPGDPKT */
#define IFX_GETH_RXICMP_GOOD_PACKETS_RXICMPGDPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXICMP_ERROR_PACKETS_Bits.RXICMPERRPKT */
#define IFX_GETH_RXICMP_ERROR_PACKETS_RXICMPERRPKT_LEN (16u)

/** \brief Mask for Ifx_GETH_RXICMP_ERROR_PACKETS_Bits.RXICMPERRPKT */
#define IFX_GETH_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_RXICMP_ERROR_PACKETS_Bits.RXICMPERRPKT */
#define IFX_GETH_RXICMP_ERROR_PACKETS_RXICMPERRPKT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV4_GOOD_OCTETS_Bits.RXIPV4GDOCT */
#define IFX_GETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXIPV4_GOOD_OCTETS_Bits.RXIPV4GDOCT */
#define IFX_GETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXIPV4_GOOD_OCTETS_Bits.RXIPV4GDOCT */
#define IFX_GETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV4_HEADER_ERROR_OCTETS_Bits.RXIPV4HDRERROCT */
#define IFX_GETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXIPV4_HEADER_ERROR_OCTETS_Bits.RXIPV4HDRERROCT */
#define IFX_GETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXIPV4_HEADER_ERROR_OCTETS_Bits.RXIPV4HDRERROCT */
#define IFX_GETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV4_NO_PAYLOAD_OCTETS_Bits.RXIPV4NOPAYOCT */
#define IFX_GETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXIPV4_NO_PAYLOAD_OCTETS_Bits.RXIPV4NOPAYOCT */
#define IFX_GETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXIPV4_NO_PAYLOAD_OCTETS_Bits.RXIPV4NOPAYOCT */
#define IFX_GETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV4_FRAGMENTED_OCTETS_Bits.RXIPV4FRAGOCT */
#define IFX_GETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXIPV4_FRAGMENTED_OCTETS_Bits.RXIPV4FRAGOCT */
#define IFX_GETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXIPV4_FRAGMENTED_OCTETS_Bits.RXIPV4FRAGOCT */
#define IFX_GETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_Bits.RXIPV4UDSBLOCT */
#define IFX_GETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_Bits.RXIPV4UDSBLOCT */
#define IFX_GETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_Bits.RXIPV4UDSBLOCT */
#define IFX_GETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV6_GOOD_OCTETS_Bits.RXIPV6GDOCT */
#define IFX_GETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXIPV6_GOOD_OCTETS_Bits.RXIPV6GDOCT */
#define IFX_GETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXIPV6_GOOD_OCTETS_Bits.RXIPV6GDOCT */
#define IFX_GETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV6_HEADER_ERROR_OCTETS_Bits.RXIPV6HDRERROCT */
#define IFX_GETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXIPV6_HEADER_ERROR_OCTETS_Bits.RXIPV6HDRERROCT */
#define IFX_GETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXIPV6_HEADER_ERROR_OCTETS_Bits.RXIPV6HDRERROCT */
#define IFX_GETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXIPV6_NO_PAYLOAD_OCTETS_Bits.RXIPV6NOPAYOCT */
#define IFX_GETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXIPV6_NO_PAYLOAD_OCTETS_Bits.RXIPV6NOPAYOCT */
#define IFX_GETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXIPV6_NO_PAYLOAD_OCTETS_Bits.RXIPV6NOPAYOCT */
#define IFX_GETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXUDP_GOOD_OCTETS_Bits.RXUDPGDOCT */
#define IFX_GETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXUDP_GOOD_OCTETS_Bits.RXUDPGDOCT */
#define IFX_GETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXUDP_GOOD_OCTETS_Bits.RXUDPGDOCT */
#define IFX_GETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXUDP_ERROR_OCTETS_Bits.RXUDPERROCT */
#define IFX_GETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXUDP_ERROR_OCTETS_Bits.RXUDPERROCT */
#define IFX_GETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXUDP_ERROR_OCTETS_Bits.RXUDPERROCT */
#define IFX_GETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXTCP_GOOD_OCTETS_Bits.RXTCPGDOCT */
#define IFX_GETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXTCP_GOOD_OCTETS_Bits.RXTCPGDOCT */
#define IFX_GETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXTCP_GOOD_OCTETS_Bits.RXTCPGDOCT */
#define IFX_GETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXTCP_ERROR_OCTETS_Bits.RXTCPERROCT */
#define IFX_GETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXTCP_ERROR_OCTETS_Bits.RXTCPERROCT */
#define IFX_GETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXTCP_ERROR_OCTETS_Bits.RXTCPERROCT */
#define IFX_GETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXICMP_GOOD_OCTETS_Bits.RXICMPGDOCT */
#define IFX_GETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXICMP_GOOD_OCTETS_Bits.RXICMPGDOCT */
#define IFX_GETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXICMP_GOOD_OCTETS_Bits.RXICMPGDOCT */
#define IFX_GETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_OFF (0u)

/** \brief Length for Ifx_GETH_RXICMP_ERROR_OCTETS_Bits.RXICMPERROCT */
#define IFX_GETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_LEN (32u)

/** \brief Mask for Ifx_GETH_RXICMP_ERROR_OCTETS_Bits.RXICMPERROCT */
#define IFX_GETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_RXICMP_ERROR_OCTETS_Bits.RXICMPERROCT */
#define IFX_GETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSENA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSENA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSENA_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSCFUPDT */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSCFUPDT_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSCFUPDT */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSCFUPDT */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSCFUPDT_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSINIT */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSINIT_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSINIT */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSINIT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSINIT */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSINIT_OFF (2u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSUPDT */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSUPDT_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSUPDT */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSUPDT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSUPDT */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSUPDT_OFF (3u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSADDREG */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSADDREG_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSADDREG */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSADDREG_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSADDREG */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSADDREG_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSENALL */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSENALL_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSENALL */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSENALL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSENALL */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSENALL_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSCTRLSSR */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSCTRLSSR */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSCTRLSSR */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_OFF (9u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSVER2ENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSVER2ENA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSVER2ENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSVER2ENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSVER2ENA_OFF (10u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSIPENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSIPENA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSIPENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSIPENA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSIPENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSIPENA_OFF (11u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSIPV6ENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSIPV6ENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSIPV6ENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_OFF (12u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSIPV4ENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSIPV4ENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSIPV4ENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_OFF (13u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSEVNTENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSEVNTENA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSEVNTENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSEVNTENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSEVNTENA_OFF (14u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSMSTRENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSMSTRENA_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSMSTRENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSMSTRENA */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSMSTRENA_OFF (15u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.SNAPTYPSEL */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.SNAPTYPSEL */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.SNAPTYPSEL */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSENMACADDR */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSENMACADDR_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSENMACADDR */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TSENMACADDR */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TSENMACADDR_OFF (18u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.CSC */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_CSC_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.CSC */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_CSC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.CSC */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_CSC_OFF (19u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TXTSSTSM */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TXTSSTSM_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TXTSSTSM */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.TXTSSTSM */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_TXTSSTSM_OFF (24u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.AV8021ASMEN */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.AV8021ASMEN */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_CONTROL_Bits.AV8021ASMEN */
#define IFX_GETH_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_OFF (28u)

/** \brief Length for Ifx_GETH_MAC_SUB_SECOND_INCREMENT_Bits.SNSINC */
#define IFX_GETH_MAC_SUB_SECOND_INCREMENT_SNSINC_LEN (8u)

/** \brief Mask for Ifx_GETH_MAC_SUB_SECOND_INCREMENT_Bits.SNSINC */
#define IFX_GETH_MAC_SUB_SECOND_INCREMENT_SNSINC_MSK (0xffu)

/** \brief Offset for Ifx_GETH_MAC_SUB_SECOND_INCREMENT_Bits.SNSINC */
#define IFX_GETH_MAC_SUB_SECOND_INCREMENT_SNSINC_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_SUB_SECOND_INCREMENT_Bits.SSINC */
#define IFX_GETH_MAC_SUB_SECOND_INCREMENT_SSINC_LEN (8u)

/** \brief Mask for Ifx_GETH_MAC_SUB_SECOND_INCREMENT_Bits.SSINC */
#define IFX_GETH_MAC_SUB_SECOND_INCREMENT_SSINC_MSK (0xffu)

/** \brief Offset for Ifx_GETH_MAC_SUB_SECOND_INCREMENT_Bits.SSINC */
#define IFX_GETH_MAC_SUB_SECOND_INCREMENT_SSINC_OFF (16u)

/** \brief Length for Ifx_GETH_MAC_SYSTEM_TIME_SECONDS_Bits.TSS */
#define IFX_GETH_MAC_SYSTEM_TIME_SECONDS_TSS_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_SYSTEM_TIME_SECONDS_Bits.TSS */
#define IFX_GETH_MAC_SYSTEM_TIME_SECONDS_TSS_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_SYSTEM_TIME_SECONDS_Bits.TSS */
#define IFX_GETH_MAC_SYSTEM_TIME_SECONDS_TSS_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_SYSTEM_TIME_NANOSECONDS_Bits.TSSS */
#define IFX_GETH_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_LEN (31u)

/** \brief Mask for Ifx_GETH_MAC_SYSTEM_TIME_NANOSECONDS_Bits.TSSS */
#define IFX_GETH_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MSK (0x7fffffffu)

/** \brief Offset for Ifx_GETH_MAC_SYSTEM_TIME_NANOSECONDS_Bits.TSSS */
#define IFX_GETH_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_SYSTEM_TIME_SECONDS_UPDATE_Bits.TSS */
#define IFX_GETH_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_SYSTEM_TIME_SECONDS_UPDATE_Bits.TSS */
#define IFX_GETH_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_SYSTEM_TIME_SECONDS_UPDATE_Bits.TSS */
#define IFX_GETH_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.TSSS */
#define IFX_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_LEN (31u)

/** \brief Mask for Ifx_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.TSSS */
#define IFX_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MSK (0x7fffffffu)

/** \brief Offset for Ifx_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.TSSS */
#define IFX_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.ADDSUB */
#define IFX_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.ADDSUB */
#define IFX_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_Bits.ADDSUB */
#define IFX_GETH_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_OFF (31u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_ADDEND_Bits.TSAR */
#define IFX_GETH_MAC_TIMESTAMP_ADDEND_TSAR_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_ADDEND_Bits.TSAR */
#define IFX_GETH_MAC_TIMESTAMP_ADDEND_TSAR_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_ADDEND_Bits.TSAR */
#define IFX_GETH_MAC_TIMESTAMP_ADDEND_TSAR_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_Bits.TSHWR */
#define IFX_GETH_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_LEN (16u)

/** \brief Mask for Ifx_GETH_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_Bits.TSHWR */
#define IFX_GETH_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_Bits.TSHWR */
#define IFX_GETH_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSSOVF */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSSOVF_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSSOVF */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSSOVF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSSOVF */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSSOVF_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT0 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT0_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT0 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT0_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT0 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT0_OFF (1u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR0 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR0_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR0 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR0 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR0_OFF (3u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT1 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT1_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT1 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT1_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT1 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT1_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR1 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR1_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR1 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR1 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR1_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT2 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT2_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT2 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT2_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT2 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT2_OFF (6u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR2 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR2_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR2 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR2 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR2_OFF (7u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT3 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT3_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT3 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT3_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTARGT3 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTARGT3_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR3 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR3_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR3 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TSTRGTERR3 */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TSTRGTERR3_OFF (9u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TXTSSIS */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TXTSSIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TXTSSIS */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TXTSSIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_STATUS_Bits.TXTSSIS */
#define IFX_GETH_MAC_TIMESTAMP_STATUS_TXTSSIS_OFF (15u)

/** \brief Length for Ifx_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_Bits.TXTSSLO */
#define IFX_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_LEN (31u)

/** \brief Mask for Ifx_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_Bits.TXTSSLO */
#define IFX_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MSK (0x7fffffffu)

/** \brief Offset for Ifx_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_Bits.TXTSSLO */
#define IFX_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_Bits.TXTSSMIS */
#define IFX_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_Bits.TXTSSMIS */
#define IFX_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_Bits.TXTSSMIS */
#define IFX_GETH_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_OFF (31u)

/** \brief Length for Ifx_GETH_MAC_TX_TIMESTAMP_STATUS_SECONDS_Bits.TXTSSHI */
#define IFX_GETH_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_TX_TIMESTAMP_STATUS_SECONDS_Bits.TXTSSHI */
#define IFX_GETH_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_TX_TIMESTAMP_STATUS_SECONDS_Bits.TXTSSHI */
#define IFX_GETH_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_INGRESS_ASYM_CORR_Bits.OSTIAC */
#define IFX_GETH_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_INGRESS_ASYM_CORR_Bits.OSTIAC */
#define IFX_GETH_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_INGRESS_ASYM_CORR_Bits.OSTIAC */
#define IFX_GETH_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_EGRESS_ASYM_CORR_Bits.OSTEAC */
#define IFX_GETH_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_EGRESS_ASYM_CORR_Bits.OSTEAC */
#define IFX_GETH_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_EGRESS_ASYM_CORR_Bits.OSTEAC */
#define IFX_GETH_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_Bits.TSIC */
#define IFX_GETH_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_Bits.TSIC */
#define IFX_GETH_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_Bits.TSIC */
#define IFX_GETH_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_Bits.TSEC */
#define IFX_GETH_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_Bits.TSEC */
#define IFX_GETH_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_Bits.TSEC */
#define IFX_GETH_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_Bits.TSICSNS */
#define IFX_GETH_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_LEN (8u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_Bits.TSICSNS */
#define IFX_GETH_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MSK (0xffu)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_Bits.TSICSNS */
#define IFX_GETH_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_Bits.TSECSNS */
#define IFX_GETH_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_LEN (8u)

/** \brief Mask for Ifx_GETH_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_Bits.TSECSNS */
#define IFX_GETH_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MSK (0xffu)

/** \brief Offset for Ifx_GETH_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_Bits.TSECSNS */
#define IFX_GETH_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_OFF (8u)

/** \brief Length for Ifx_GETH_MAC_PPS_CONTROL_Bits.PPSCTRL_PPSCMD */
#define IFX_GETH_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_LEN (4u)

/** \brief Mask for Ifx_GETH_MAC_PPS_CONTROL_Bits.PPSCTRL_PPSCMD */
#define IFX_GETH_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MAC_PPS_CONTROL_Bits.PPSCTRL_PPSCMD */
#define IFX_GETH_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_PPS_CONTROL_Bits.PPSEN0 */
#define IFX_GETH_MAC_PPS_CONTROL_PPSEN0_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PPS_CONTROL_Bits.PPSEN0 */
#define IFX_GETH_MAC_PPS_CONTROL_PPSEN0_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PPS_CONTROL_Bits.PPSEN0 */
#define IFX_GETH_MAC_PPS_CONTROL_PPSEN0_OFF (4u)

/** \brief Length for Ifx_GETH_MAC_PPS_CONTROL_Bits.TRGTMODSEL0 */
#define IFX_GETH_MAC_PPS_CONTROL_TRGTMODSEL0_LEN (2u)

/** \brief Mask for Ifx_GETH_MAC_PPS_CONTROL_Bits.TRGTMODSEL0 */
#define IFX_GETH_MAC_PPS_CONTROL_TRGTMODSEL0_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MAC_PPS_CONTROL_Bits.TRGTMODSEL0 */
#define IFX_GETH_MAC_PPS_CONTROL_TRGTMODSEL0_OFF (5u)

/** \brief Length for Ifx_GETH_MAC_PPS0_TARGET_TIME_SECONDS_Bits.TSTRH0 */
#define IFX_GETH_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_PPS0_TARGET_TIME_SECONDS_Bits.TSTRH0 */
#define IFX_GETH_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_PPS0_TARGET_TIME_SECONDS_Bits.TSTRH0 */
#define IFX_GETH_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_Bits.TTSL0 */
#define IFX_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_LEN (31u)

/** \brief Mask for Ifx_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_Bits.TTSL0 */
#define IFX_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MSK (0x7fffffffu)

/** \brief Offset for Ifx_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_Bits.TTSL0 */
#define IFX_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_Bits.TRGTBUSY0 */
#define IFX_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_LEN (1u)

/** \brief Mask for Ifx_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_Bits.TRGTBUSY0 */
#define IFX_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_Bits.TRGTBUSY0 */
#define IFX_GETH_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_OFF (31u)

/** \brief Length for Ifx_GETH_MAC_PPS0_INTERVAL_Bits.PPSINT0 */
#define IFX_GETH_MAC_PPS0_INTERVAL_PPSINT0_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_PPS0_INTERVAL_Bits.PPSINT0 */
#define IFX_GETH_MAC_PPS0_INTERVAL_PPSINT0_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_PPS0_INTERVAL_Bits.PPSINT0 */
#define IFX_GETH_MAC_PPS0_INTERVAL_PPSINT0_OFF (0u)

/** \brief Length for Ifx_GETH_MAC_PPS0_WIDTH_Bits.PPSWIDTH0 */
#define IFX_GETH_MAC_PPS0_WIDTH_PPSWIDTH0_LEN (32u)

/** \brief Mask for Ifx_GETH_MAC_PPS0_WIDTH_Bits.PPSWIDTH0 */
#define IFX_GETH_MAC_PPS0_WIDTH_PPSWIDTH0_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_MAC_PPS0_WIDTH_Bits.PPSWIDTH0 */
#define IFX_GETH_MAC_PPS0_WIDTH_PPSWIDTH0_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_OPERATION_MODE_Bits.DTXSTS */
#define IFX_GETH_MTL_OPERATION_MODE_DTXSTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_OPERATION_MODE_Bits.DTXSTS */
#define IFX_GETH_MTL_OPERATION_MODE_DTXSTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_OPERATION_MODE_Bits.DTXSTS */
#define IFX_GETH_MTL_OPERATION_MODE_DTXSTS_OFF (1u)

/** \brief Length for Ifx_GETH_MTL_OPERATION_MODE_Bits.RAA */
#define IFX_GETH_MTL_OPERATION_MODE_RAA_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_OPERATION_MODE_Bits.RAA */
#define IFX_GETH_MTL_OPERATION_MODE_RAA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_OPERATION_MODE_Bits.RAA */
#define IFX_GETH_MTL_OPERATION_MODE_RAA_OFF (2u)

/** \brief Length for Ifx_GETH_MTL_OPERATION_MODE_Bits.SCHALG */
#define IFX_GETH_MTL_OPERATION_MODE_SCHALG_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_OPERATION_MODE_Bits.SCHALG */
#define IFX_GETH_MTL_OPERATION_MODE_SCHALG_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_OPERATION_MODE_Bits.SCHALG */
#define IFX_GETH_MTL_OPERATION_MODE_SCHALG_OFF (5u)

/** \brief Length for Ifx_GETH_MTL_OPERATION_MODE_Bits.CNTPRST */
#define IFX_GETH_MTL_OPERATION_MODE_CNTPRST_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_OPERATION_MODE_Bits.CNTPRST */
#define IFX_GETH_MTL_OPERATION_MODE_CNTPRST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_OPERATION_MODE_Bits.CNTPRST */
#define IFX_GETH_MTL_OPERATION_MODE_CNTPRST_OFF (8u)

/** \brief Length for Ifx_GETH_MTL_OPERATION_MODE_Bits.CNTCLR */
#define IFX_GETH_MTL_OPERATION_MODE_CNTCLR_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_OPERATION_MODE_Bits.CNTCLR */
#define IFX_GETH_MTL_OPERATION_MODE_CNTCLR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_OPERATION_MODE_Bits.CNTCLR */
#define IFX_GETH_MTL_OPERATION_MODE_CNTCLR_OFF (9u)

/** \brief Length for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q0IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q0IS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q0IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q0IS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q0IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q0IS_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q1IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q1IS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q1IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q1IS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q1IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q1IS_OFF (1u)

/** \brief Length for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q2IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q2IS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q2IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q2IS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q2IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q2IS_OFF (2u)

/** \brief Length for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q3IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q3IS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q3IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q3IS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_INTERRUPT_STATUS_Bits.Q3IS */
#define IFX_GETH_MTL_INTERRUPT_STATUS_Q3IS_OFF (3u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q0MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q0MDMACH_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q0MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q0MDMACH_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q0MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q0MDMACH_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q0DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q0DDMACH_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q0DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q0DDMACH_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q0DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q0DDMACH_OFF (4u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q1MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q1MDMACH_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q1MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q1MDMACH_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q1MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q1MDMACH_OFF (8u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q1DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q1DDMACH_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q1DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q1DDMACH_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q1DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q1DDMACH_OFF (12u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q2MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q2MDMACH_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q2MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q2MDMACH_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q2MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q2MDMACH_OFF (16u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q2DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q2DDMACH_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q2DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q2DDMACH_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q2DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q2DDMACH_OFF (20u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q3MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q3MDMACH_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q3MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q3MDMACH_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q3MDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q3MDMACH_OFF (24u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q3DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q3DDMACH_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q3DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q3DDMACH_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DMA_MAP0_Bits.Q3DDMACH */
#define IFX_GETH_MTL_RXQ_DMA_MAP0_Q3DDMACH_OFF (28u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.FTQ */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_FTQ_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.FTQ */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_FTQ_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.FTQ */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_FTQ_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TSF */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TSF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TSF */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TSF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TSF */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TSF_OFF (1u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TXQEN */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TXQEN_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TXQEN */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TXQEN_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TXQEN */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TXQEN_OFF (2u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TTC */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TTC_LEN (3u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TTC */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TTC_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TTC */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TTC_OFF (4u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TQS */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TQS_LEN (4u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TQS */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TQS_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_OPERATION_MODE_Bits.TQS */
#define IFX_GETH_MTL_TXQ0_OPERATION_MODE_TQS_OFF (16u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_UNDERFLOW_Bits.UFFRMCNT */
#define IFX_GETH_MTL_TXQ0_UNDERFLOW_UFFRMCNT_LEN (11u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_UNDERFLOW_Bits.UFFRMCNT */
#define IFX_GETH_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MSK (0x7ffu)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_UNDERFLOW_Bits.UFFRMCNT */
#define IFX_GETH_MTL_TXQ0_UNDERFLOW_UFFRMCNT_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_UNDERFLOW_Bits.UFCNTOVF */
#define IFX_GETH_MTL_TXQ0_UNDERFLOW_UFCNTOVF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_UNDERFLOW_Bits.UFCNTOVF */
#define IFX_GETH_MTL_TXQ0_UNDERFLOW_UFCNTOVF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_UNDERFLOW_Bits.UFCNTOVF */
#define IFX_GETH_MTL_TXQ0_UNDERFLOW_UFCNTOVF_OFF (11u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TXQPAUSED */
#define IFX_GETH_MTL_TXQ0_DEBUG_TXQPAUSED_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TXQPAUSED */
#define IFX_GETH_MTL_TXQ0_DEBUG_TXQPAUSED_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TXQPAUSED */
#define IFX_GETH_MTL_TXQ0_DEBUG_TXQPAUSED_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TRCSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TRCSTS_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TRCSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TRCSTS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TRCSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TRCSTS_OFF (1u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TWCSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TWCSTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TWCSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TWCSTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TWCSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TWCSTS_OFF (3u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TXQSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TXQSTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TXQSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TXQSTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TXQSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TXQSTS_OFF (4u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TXSTSFSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TXSTSFSTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TXSTSFSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TXSTSFSTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.TXSTSFSTS */
#define IFX_GETH_MTL_TXQ0_DEBUG_TXSTSFSTS_OFF (5u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.PTXQ */
#define IFX_GETH_MTL_TXQ0_DEBUG_PTXQ_LEN (3u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.PTXQ */
#define IFX_GETH_MTL_TXQ0_DEBUG_PTXQ_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.PTXQ */
#define IFX_GETH_MTL_TXQ0_DEBUG_PTXQ_OFF (16u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.STXSTSF */
#define IFX_GETH_MTL_TXQ0_DEBUG_STXSTSF_LEN (3u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.STXSTSF */
#define IFX_GETH_MTL_TXQ0_DEBUG_STXSTSF_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_DEBUG_Bits.STXSTSF */
#define IFX_GETH_MTL_TXQ0_DEBUG_STXSTSF_OFF (20u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_ETS_STATUS_Bits.ABS */
#define IFX_GETH_MTL_TXQ0_ETS_STATUS_ABS_LEN (24u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_ETS_STATUS_Bits.ABS */
#define IFX_GETH_MTL_TXQ0_ETS_STATUS_ABS_MSK (0xffffffu)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_ETS_STATUS_Bits.ABS */
#define IFX_GETH_MTL_TXQ0_ETS_STATUS_ABS_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_TXQ0_QUANTUM_WEIGHT_Bits.ISCQW */
#define IFX_GETH_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_LEN (21u)

/** \brief Mask for Ifx_GETH_MTL_TXQ0_QUANTUM_WEIGHT_Bits.ISCQW */
#define IFX_GETH_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MSK (0x1fffffu)

/** \brief Offset for Ifx_GETH_MTL_TXQ0_QUANTUM_WEIGHT_Bits.ISCQW */
#define IFX_GETH_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.TXUNFIS */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.TXUNFIS */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.TXUNFIS */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.ABPSIS */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.ABPSIS */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.ABPSIS */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIS_OFF (1u)

/** \brief Length for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.TXUIE */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.TXUIE */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.TXUIE */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUIE_OFF (8u)

/** \brief Length for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.ABPSIE */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.ABPSIE */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.ABPSIE */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_ABPSIE_OFF (9u)

/** \brief Length for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.RXOVFIS */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.RXOVFIS */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.RXOVFIS */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOVFIS_OFF (16u)

/** \brief Length for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.RXOIE */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.RXOIE */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_Bits.RXOIE */
#define IFX_GETH_MTL_Q0_INTERRUPT_CONTROL_STATUS_RXOIE_OFF (24u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RTC */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RTC_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RTC */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RTC_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RTC */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RTC_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.FUP */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_FUP_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.FUP */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_FUP_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.FUP */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_FUP_OFF (3u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.FEP */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_FEP_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.FEP */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_FEP_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.FEP */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_FEP_OFF (4u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RSF */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RSF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RSF */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RSF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RSF */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RSF_OFF (5u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.DIS_TCP_EF */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.DIS_TCP_EF */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.DIS_TCP_EF */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF_OFF (6u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.EHFC */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_EHFC_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.EHFC */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_EHFC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.EHFC */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_EHFC_OFF (7u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RFA */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RFA_LEN (4u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RFA */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RFA_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RFA */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RFA_OFF (8u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RFD */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RFD_LEN (4u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RFD */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RFD_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RFD */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RFD_OFF (14u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RQS */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RQS_LEN (5u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RQS */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RQS_MSK (0x1fu)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_OPERATION_MODE_Bits.RQS */
#define IFX_GETH_MTL_RXQ0_OPERATION_MODE_RQS_OFF (20u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFPKTCNT */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_LEN (11u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFPKTCNT */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MSK (0x7ffu)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFPKTCNT */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFCNTOVF */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFCNTOVF */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFCNTOVF */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_OFF (11u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.MISPKTCNT */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_LEN (11u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.MISPKTCNT */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MSK (0x7ffu)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.MISPKTCNT */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_OFF (16u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.MISCNTOVF */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.MISCNTOVF */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_Bits.MISCNTOVF */
#define IFX_GETH_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_OFF (27u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.RWCSTS */
#define IFX_GETH_MTL_RXQ0_DEBUG_RWCSTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.RWCSTS */
#define IFX_GETH_MTL_RXQ0_DEBUG_RWCSTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.RWCSTS */
#define IFX_GETH_MTL_RXQ0_DEBUG_RWCSTS_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.RRCSTS */
#define IFX_GETH_MTL_RXQ0_DEBUG_RRCSTS_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.RRCSTS */
#define IFX_GETH_MTL_RXQ0_DEBUG_RRCSTS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.RRCSTS */
#define IFX_GETH_MTL_RXQ0_DEBUG_RRCSTS_OFF (1u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.RXQSTS */
#define IFX_GETH_MTL_RXQ0_DEBUG_RXQSTS_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.RXQSTS */
#define IFX_GETH_MTL_RXQ0_DEBUG_RXQSTS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.RXQSTS */
#define IFX_GETH_MTL_RXQ0_DEBUG_RXQSTS_OFF (4u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.PRXQ */
#define IFX_GETH_MTL_RXQ0_DEBUG_PRXQ_LEN (14u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.PRXQ */
#define IFX_GETH_MTL_RXQ0_DEBUG_PRXQ_MSK (0x3fffu)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_DEBUG_Bits.PRXQ */
#define IFX_GETH_MTL_RXQ0_DEBUG_PRXQ_OFF (16u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_CONTROL_Bits.RXQ_WEGT */
#define IFX_GETH_MTL_RXQ0_CONTROL_RXQ_WEGT_LEN (3u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_CONTROL_Bits.RXQ_WEGT */
#define IFX_GETH_MTL_RXQ0_CONTROL_RXQ_WEGT_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_CONTROL_Bits.RXQ_WEGT */
#define IFX_GETH_MTL_RXQ0_CONTROL_RXQ_WEGT_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_RXQ0_CONTROL_Bits.RXQ_FRM_ARBIT */
#define IFX_GETH_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ0_CONTROL_Bits.RXQ_FRM_ARBIT */
#define IFX_GETH_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ0_CONTROL_Bits.RXQ_FRM_ARBIT */
#define IFX_GETH_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT_OFF (3u)

/** \brief Length for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.FTQ */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_FTQ_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.FTQ */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_FTQ_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.FTQ */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_FTQ_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TSF */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TSF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TSF */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TSF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TSF */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TSF_OFF (1u)

/** \brief Length for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TXQEN */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TXQEN_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TXQEN */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TXQEN_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TXQEN */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TXQEN_OFF (2u)

/** \brief Length for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TTC */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TTC_LEN (3u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TTC */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TTC_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TTC */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TTC_OFF (4u)

/** \brief Length for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TQS */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TQS_LEN (4u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TQS */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TQS_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MTL_TXQ_OPERATION_MODE_Bits.TQS */
#define IFX_GETH_MTL_TXQ_OPERATION_MODE_TQS_OFF (16u)

/** \brief Length for Ifx_GETH_MTL_TXQ_UNDERFLOW_Bits.UFFRMCNT */
#define IFX_GETH_MTL_TXQ_UNDERFLOW_UFFRMCNT_LEN (11u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_UNDERFLOW_Bits.UFFRMCNT */
#define IFX_GETH_MTL_TXQ_UNDERFLOW_UFFRMCNT_MSK (0x7ffu)

/** \brief Offset for Ifx_GETH_MTL_TXQ_UNDERFLOW_Bits.UFFRMCNT */
#define IFX_GETH_MTL_TXQ_UNDERFLOW_UFFRMCNT_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_TXQ_UNDERFLOW_Bits.UFCNTOVF */
#define IFX_GETH_MTL_TXQ_UNDERFLOW_UFCNTOVF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_UNDERFLOW_Bits.UFCNTOVF */
#define IFX_GETH_MTL_TXQ_UNDERFLOW_UFCNTOVF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_UNDERFLOW_Bits.UFCNTOVF */
#define IFX_GETH_MTL_TXQ_UNDERFLOW_UFCNTOVF_OFF (11u)

/** \brief Length for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TXQPAUSED */
#define IFX_GETH_MTL_TXQ_DEBUG_TXQPAUSED_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TXQPAUSED */
#define IFX_GETH_MTL_TXQ_DEBUG_TXQPAUSED_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TXQPAUSED */
#define IFX_GETH_MTL_TXQ_DEBUG_TXQPAUSED_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TRCSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TRCSTS_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TRCSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TRCSTS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TRCSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TRCSTS_OFF (1u)

/** \brief Length for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TWCSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TWCSTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TWCSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TWCSTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TWCSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TWCSTS_OFF (3u)

/** \brief Length for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TXQSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TXQSTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TXQSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TXQSTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TXQSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TXQSTS_OFF (4u)

/** \brief Length for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TXSTSFSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TXSTSFSTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TXSTSFSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TXSTSFSTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_DEBUG_Bits.TXSTSFSTS */
#define IFX_GETH_MTL_TXQ_DEBUG_TXSTSFSTS_OFF (5u)

/** \brief Length for Ifx_GETH_MTL_TXQ_DEBUG_Bits.PTXQ */
#define IFX_GETH_MTL_TXQ_DEBUG_PTXQ_LEN (3u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_DEBUG_Bits.PTXQ */
#define IFX_GETH_MTL_TXQ_DEBUG_PTXQ_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_DEBUG_Bits.PTXQ */
#define IFX_GETH_MTL_TXQ_DEBUG_PTXQ_OFF (16u)

/** \brief Length for Ifx_GETH_MTL_TXQ_DEBUG_Bits.STXSTSF */
#define IFX_GETH_MTL_TXQ_DEBUG_STXSTSF_LEN (3u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_DEBUG_Bits.STXSTSF */
#define IFX_GETH_MTL_TXQ_DEBUG_STXSTSF_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_DEBUG_Bits.STXSTSF */
#define IFX_GETH_MTL_TXQ_DEBUG_STXSTSF_OFF (20u)

/** \brief Length for Ifx_GETH_MTL_TXQ_ETS_CONTROL_Bits.AVALG */
#define IFX_GETH_MTL_TXQ_ETS_CONTROL_AVALG_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_ETS_CONTROL_Bits.AVALG */
#define IFX_GETH_MTL_TXQ_ETS_CONTROL_AVALG_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_ETS_CONTROL_Bits.AVALG */
#define IFX_GETH_MTL_TXQ_ETS_CONTROL_AVALG_OFF (2u)

/** \brief Length for Ifx_GETH_MTL_TXQ_ETS_CONTROL_Bits.CC */
#define IFX_GETH_MTL_TXQ_ETS_CONTROL_CC_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_ETS_CONTROL_Bits.CC */
#define IFX_GETH_MTL_TXQ_ETS_CONTROL_CC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_ETS_CONTROL_Bits.CC */
#define IFX_GETH_MTL_TXQ_ETS_CONTROL_CC_OFF (3u)

/** \brief Length for Ifx_GETH_MTL_TXQ_ETS_CONTROL_Bits.SLC */
#define IFX_GETH_MTL_TXQ_ETS_CONTROL_SLC_LEN (3u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_ETS_CONTROL_Bits.SLC */
#define IFX_GETH_MTL_TXQ_ETS_CONTROL_SLC_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MTL_TXQ_ETS_CONTROL_Bits.SLC */
#define IFX_GETH_MTL_TXQ_ETS_CONTROL_SLC_OFF (4u)

/** \brief Length for Ifx_GETH_MTL_TXQ_ETS_STATUS_Bits.ABS */
#define IFX_GETH_MTL_TXQ_ETS_STATUS_ABS_LEN (24u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_ETS_STATUS_Bits.ABS */
#define IFX_GETH_MTL_TXQ_ETS_STATUS_ABS_MSK (0xffffffu)

/** \brief Offset for Ifx_GETH_MTL_TXQ_ETS_STATUS_Bits.ABS */
#define IFX_GETH_MTL_TXQ_ETS_STATUS_ABS_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_TXQ_QUANTUM_WEIGHT_Bits.ISCQW */
#define IFX_GETH_MTL_TXQ_QUANTUM_WEIGHT_ISCQW_LEN (21u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_QUANTUM_WEIGHT_Bits.ISCQW */
#define IFX_GETH_MTL_TXQ_QUANTUM_WEIGHT_ISCQW_MSK (0x1fffffu)

/** \brief Offset for Ifx_GETH_MTL_TXQ_QUANTUM_WEIGHT_Bits.ISCQW */
#define IFX_GETH_MTL_TXQ_QUANTUM_WEIGHT_ISCQW_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_TXQ_SENDSLOPECREDIT_Bits.SSC */
#define IFX_GETH_MTL_TXQ_SENDSLOPECREDIT_SSC_LEN (14u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_SENDSLOPECREDIT_Bits.SSC */
#define IFX_GETH_MTL_TXQ_SENDSLOPECREDIT_SSC_MSK (0x3fffu)

/** \brief Offset for Ifx_GETH_MTL_TXQ_SENDSLOPECREDIT_Bits.SSC */
#define IFX_GETH_MTL_TXQ_SENDSLOPECREDIT_SSC_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_TXQ_HICREDIT_Bits.HC */
#define IFX_GETH_MTL_TXQ_HICREDIT_HC_LEN (29u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_HICREDIT_Bits.HC */
#define IFX_GETH_MTL_TXQ_HICREDIT_HC_MSK (0x1fffffffu)

/** \brief Offset for Ifx_GETH_MTL_TXQ_HICREDIT_Bits.HC */
#define IFX_GETH_MTL_TXQ_HICREDIT_HC_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_TXQ_LOCREDIT_Bits.LC */
#define IFX_GETH_MTL_TXQ_LOCREDIT_LC_LEN (29u)

/** \brief Mask for Ifx_GETH_MTL_TXQ_LOCREDIT_Bits.LC */
#define IFX_GETH_MTL_TXQ_LOCREDIT_LC_MSK (0x1fffffffu)

/** \brief Offset for Ifx_GETH_MTL_TXQ_LOCREDIT_Bits.LC */
#define IFX_GETH_MTL_TXQ_LOCREDIT_LC_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.TXUNFIS */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_TXUNFIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.TXUNFIS */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_TXUNFIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.TXUNFIS */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_TXUNFIS_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.ABPSIS */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_ABPSIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.ABPSIS */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_ABPSIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.ABPSIS */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_ABPSIS_OFF (1u)

/** \brief Length for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.TXUIE */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_TXUIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.TXUIE */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_TXUIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.TXUIE */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_TXUIE_OFF (8u)

/** \brief Length for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.ABPSIE */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_ABPSIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.ABPSIE */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_ABPSIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.ABPSIE */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_ABPSIE_OFF (9u)

/** \brief Length for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.RXOVFIS */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_RXOVFIS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.RXOVFIS */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_RXOVFIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.RXOVFIS */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_RXOVFIS_OFF (16u)

/** \brief Length for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.RXOIE */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_RXOIE_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.RXOIE */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_RXOIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_Bits.RXOIE */
#define IFX_GETH_MTL_Q_INTERRUPT_CONTROL_STATUS_RXOIE_OFF (24u)

/** \brief Length for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RTC */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RTC_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RTC */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RTC_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RTC */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RTC_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.FUP */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_FUP_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.FUP */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_FUP_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.FUP */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_FUP_OFF (3u)

/** \brief Length for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.FEP */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_FEP_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.FEP */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_FEP_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.FEP */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_FEP_OFF (4u)

/** \brief Length for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RSF */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RSF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RSF */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RSF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RSF */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RSF_OFF (5u)

/** \brief Length for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.DIS_TCP_EF */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_DIS_TCP_EF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.DIS_TCP_EF */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_DIS_TCP_EF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.DIS_TCP_EF */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_DIS_TCP_EF_OFF (6u)

/** \brief Length for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.EHFC */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_EHFC_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.EHFC */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_EHFC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.EHFC */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_EHFC_OFF (7u)

/** \brief Length for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RFA */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RFA_LEN (4u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RFA */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RFA_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RFA */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RFA_OFF (8u)

/** \brief Length for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RFD */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RFD_LEN (4u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RFD */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RFD_MSK (0xfu)

/** \brief Offset for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RFD */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RFD_OFF (14u)

/** \brief Length for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RQS */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RQS_LEN (5u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RQS */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RQS_MSK (0x1fu)

/** \brief Offset for Ifx_GETH_MTL_RXQ_OPERATION_MODE_Bits.RQS */
#define IFX_GETH_MTL_RXQ_OPERATION_MODE_RQS_OFF (20u)

/** \brief Length for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFPKTCNT */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_LEN (11u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFPKTCNT */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MSK (0x7ffu)

/** \brief Offset for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFPKTCNT */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFCNTOVF */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFCNTOVF */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.OVFCNTOVF */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF_OFF (11u)

/** \brief Length for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.MISPKTCNT */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_LEN (11u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.MISPKTCNT */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MSK (0x7ffu)

/** \brief Offset for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.MISPKTCNT */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_OFF (16u)

/** \brief Length for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.MISCNTOVF */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.MISCNTOVF */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_Bits.MISCNTOVF */
#define IFX_GETH_MTL_RXQ_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF_OFF (27u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DEBUG_Bits.RWCSTS */
#define IFX_GETH_MTL_RXQ_DEBUG_RWCSTS_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DEBUG_Bits.RWCSTS */
#define IFX_GETH_MTL_RXQ_DEBUG_RWCSTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DEBUG_Bits.RWCSTS */
#define IFX_GETH_MTL_RXQ_DEBUG_RWCSTS_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DEBUG_Bits.RRCSTS */
#define IFX_GETH_MTL_RXQ_DEBUG_RRCSTS_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DEBUG_Bits.RRCSTS */
#define IFX_GETH_MTL_RXQ_DEBUG_RRCSTS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DEBUG_Bits.RRCSTS */
#define IFX_GETH_MTL_RXQ_DEBUG_RRCSTS_OFF (1u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DEBUG_Bits.RXQSTS */
#define IFX_GETH_MTL_RXQ_DEBUG_RXQSTS_LEN (2u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DEBUG_Bits.RXQSTS */
#define IFX_GETH_MTL_RXQ_DEBUG_RXQSTS_MSK (0x3u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DEBUG_Bits.RXQSTS */
#define IFX_GETH_MTL_RXQ_DEBUG_RXQSTS_OFF (4u)

/** \brief Length for Ifx_GETH_MTL_RXQ_DEBUG_Bits.PRXQ */
#define IFX_GETH_MTL_RXQ_DEBUG_PRXQ_LEN (14u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_DEBUG_Bits.PRXQ */
#define IFX_GETH_MTL_RXQ_DEBUG_PRXQ_MSK (0x3fffu)

/** \brief Offset for Ifx_GETH_MTL_RXQ_DEBUG_Bits.PRXQ */
#define IFX_GETH_MTL_RXQ_DEBUG_PRXQ_OFF (16u)

/** \brief Length for Ifx_GETH_MTL_RXQ_CONTROL_Bits.RXQ_WEGT */
#define IFX_GETH_MTL_RXQ_CONTROL_RXQ_WEGT_LEN (3u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_CONTROL_Bits.RXQ_WEGT */
#define IFX_GETH_MTL_RXQ_CONTROL_RXQ_WEGT_MSK (0x7u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_CONTROL_Bits.RXQ_WEGT */
#define IFX_GETH_MTL_RXQ_CONTROL_RXQ_WEGT_OFF (0u)

/** \brief Length for Ifx_GETH_MTL_RXQ_CONTROL_Bits.RXQ_FRM_ARBIT */
#define IFX_GETH_MTL_RXQ_CONTROL_RXQ_FRM_ARBIT_LEN (1u)

/** \brief Mask for Ifx_GETH_MTL_RXQ_CONTROL_Bits.RXQ_FRM_ARBIT */
#define IFX_GETH_MTL_RXQ_CONTROL_RXQ_FRM_ARBIT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_MTL_RXQ_CONTROL_Bits.RXQ_FRM_ARBIT */
#define IFX_GETH_MTL_RXQ_CONTROL_RXQ_FRM_ARBIT_OFF (3u)

/** \brief Length for Ifx_GETH_DMA_MODE_Bits.SWR */
#define IFX_GETH_DMA_MODE_SWR_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_MODE_Bits.SWR */
#define IFX_GETH_DMA_MODE_SWR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_MODE_Bits.SWR */
#define IFX_GETH_DMA_MODE_SWR_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_MODE_Bits.DA */
#define IFX_GETH_DMA_MODE_DA_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_MODE_Bits.DA */
#define IFX_GETH_DMA_MODE_DA_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_MODE_Bits.DA */
#define IFX_GETH_DMA_MODE_DA_OFF (1u)

/** \brief Length for Ifx_GETH_DMA_MODE_Bits.TAA */
#define IFX_GETH_DMA_MODE_TAA_LEN (3u)

/** \brief Mask for Ifx_GETH_DMA_MODE_Bits.TAA */
#define IFX_GETH_DMA_MODE_TAA_MSK (0x7u)

/** \brief Offset for Ifx_GETH_DMA_MODE_Bits.TAA */
#define IFX_GETH_DMA_MODE_TAA_OFF (2u)

/** \brief Length for Ifx_GETH_DMA_MODE_Bits.ARBC */
#define IFX_GETH_DMA_MODE_ARBC_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_MODE_Bits.ARBC */
#define IFX_GETH_DMA_MODE_ARBC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_MODE_Bits.ARBC */
#define IFX_GETH_DMA_MODE_ARBC_OFF (9u)

/** \brief Length for Ifx_GETH_DMA_MODE_Bits.TXPR */
#define IFX_GETH_DMA_MODE_TXPR_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_MODE_Bits.TXPR */
#define IFX_GETH_DMA_MODE_TXPR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_MODE_Bits.TXPR */
#define IFX_GETH_DMA_MODE_TXPR_OFF (11u)

/** \brief Length for Ifx_GETH_DMA_MODE_Bits.PR */
#define IFX_GETH_DMA_MODE_PR_LEN (3u)

/** \brief Mask for Ifx_GETH_DMA_MODE_Bits.PR */
#define IFX_GETH_DMA_MODE_PR_MSK (0x7u)

/** \brief Offset for Ifx_GETH_DMA_MODE_Bits.PR */
#define IFX_GETH_DMA_MODE_PR_OFF (12u)

/** \brief Length for Ifx_GETH_DMA_MODE_Bits.INTM */
#define IFX_GETH_DMA_MODE_INTM_LEN (2u)

/** \brief Mask for Ifx_GETH_DMA_MODE_Bits.INTM */
#define IFX_GETH_DMA_MODE_INTM_MSK (0x3u)

/** \brief Offset for Ifx_GETH_DMA_MODE_Bits.INTM */
#define IFX_GETH_DMA_MODE_INTM_OFF (16u)

/** \brief Length for Ifx_GETH_DMA_SYSBUS_MODE_Bits.FB */
#define IFX_GETH_DMA_SYSBUS_MODE_FB_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_SYSBUS_MODE_Bits.FB */
#define IFX_GETH_DMA_SYSBUS_MODE_FB_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_SYSBUS_MODE_Bits.FB */
#define IFX_GETH_DMA_SYSBUS_MODE_FB_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_SYSBUS_MODE_Bits.AAL */
#define IFX_GETH_DMA_SYSBUS_MODE_AAL_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_SYSBUS_MODE_Bits.AAL */
#define IFX_GETH_DMA_SYSBUS_MODE_AAL_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_SYSBUS_MODE_Bits.AAL */
#define IFX_GETH_DMA_SYSBUS_MODE_AAL_OFF (12u)

/** \brief Length for Ifx_GETH_DMA_SYSBUS_MODE_Bits.MB */
#define IFX_GETH_DMA_SYSBUS_MODE_MB_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_SYSBUS_MODE_Bits.MB */
#define IFX_GETH_DMA_SYSBUS_MODE_MB_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_SYSBUS_MODE_Bits.MB */
#define IFX_GETH_DMA_SYSBUS_MODE_MB_OFF (14u)

/** \brief Length for Ifx_GETH_DMA_SYSBUS_MODE_Bits.RB */
#define IFX_GETH_DMA_SYSBUS_MODE_RB_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_SYSBUS_MODE_Bits.RB */
#define IFX_GETH_DMA_SYSBUS_MODE_RB_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_SYSBUS_MODE_Bits.RB */
#define IFX_GETH_DMA_SYSBUS_MODE_RB_OFF (15u)

/** \brief Length for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC0IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC0IS_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC0IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC0IS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC0IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC0IS_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC1IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC1IS_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC1IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC1IS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC1IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC1IS_OFF (1u)

/** \brief Length for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC2IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC2IS_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC2IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC2IS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC2IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC2IS_OFF (2u)

/** \brief Length for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC3IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC3IS_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC3IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC3IS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.DC3IS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_DC3IS_OFF (3u)

/** \brief Length for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.MTLIS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_MTLIS_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.MTLIS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_MTLIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.MTLIS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_MTLIS_OFF (16u)

/** \brief Length for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.MACIS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_MACIS_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.MACIS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_MACIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_INTERRUPT_STATUS_Bits.MACIS */
#define IFX_GETH_DMA_INTERRUPT_STATUS_MACIS_OFF (17u)

/** \brief Length for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.AXWHSTS */
#define IFX_GETH_DMA_DEBUG_STATUS0_AXWHSTS_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.AXWHSTS */
#define IFX_GETH_DMA_DEBUG_STATUS0_AXWHSTS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.AXWHSTS */
#define IFX_GETH_DMA_DEBUG_STATUS0_AXWHSTS_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.RPS0 */
#define IFX_GETH_DMA_DEBUG_STATUS0_RPS0_LEN (4u)

/** \brief Mask for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.RPS0 */
#define IFX_GETH_DMA_DEBUG_STATUS0_RPS0_MSK (0xfu)

/** \brief Offset for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.RPS0 */
#define IFX_GETH_DMA_DEBUG_STATUS0_RPS0_OFF (8u)

/** \brief Length for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.TPS0 */
#define IFX_GETH_DMA_DEBUG_STATUS0_TPS0_LEN (4u)

/** \brief Mask for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.TPS0 */
#define IFX_GETH_DMA_DEBUG_STATUS0_TPS0_MSK (0xfu)

/** \brief Offset for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.TPS0 */
#define IFX_GETH_DMA_DEBUG_STATUS0_TPS0_OFF (12u)

/** \brief Length for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.RPS1 */
#define IFX_GETH_DMA_DEBUG_STATUS0_RPS1_LEN (4u)

/** \brief Mask for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.RPS1 */
#define IFX_GETH_DMA_DEBUG_STATUS0_RPS1_MSK (0xfu)

/** \brief Offset for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.RPS1 */
#define IFX_GETH_DMA_DEBUG_STATUS0_RPS1_OFF (16u)

/** \brief Length for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.TPS1 */
#define IFX_GETH_DMA_DEBUG_STATUS0_TPS1_LEN (4u)

/** \brief Mask for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.TPS1 */
#define IFX_GETH_DMA_DEBUG_STATUS0_TPS1_MSK (0xfu)

/** \brief Offset for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.TPS1 */
#define IFX_GETH_DMA_DEBUG_STATUS0_TPS1_OFF (20u)

/** \brief Length for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.RPS2 */
#define IFX_GETH_DMA_DEBUG_STATUS0_RPS2_LEN (4u)

/** \brief Mask for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.RPS2 */
#define IFX_GETH_DMA_DEBUG_STATUS0_RPS2_MSK (0xfu)

/** \brief Offset for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.RPS2 */
#define IFX_GETH_DMA_DEBUG_STATUS0_RPS2_OFF (24u)

/** \brief Length for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.TPS2 */
#define IFX_GETH_DMA_DEBUG_STATUS0_TPS2_LEN (4u)

/** \brief Mask for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.TPS2 */
#define IFX_GETH_DMA_DEBUG_STATUS0_TPS2_MSK (0xfu)

/** \brief Offset for Ifx_GETH_DMA_DEBUG_STATUS0_Bits.TPS2 */
#define IFX_GETH_DMA_DEBUG_STATUS0_TPS2_OFF (28u)

/** \brief Length for Ifx_GETH_DMA_DEBUG_STATUS1_Bits.RPS3 */
#define IFX_GETH_DMA_DEBUG_STATUS1_RPS3_LEN (4u)

/** \brief Mask for Ifx_GETH_DMA_DEBUG_STATUS1_Bits.RPS3 */
#define IFX_GETH_DMA_DEBUG_STATUS1_RPS3_MSK (0xfu)

/** \brief Offset for Ifx_GETH_DMA_DEBUG_STATUS1_Bits.RPS3 */
#define IFX_GETH_DMA_DEBUG_STATUS1_RPS3_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_DEBUG_STATUS1_Bits.TPS3 */
#define IFX_GETH_DMA_DEBUG_STATUS1_TPS3_LEN (4u)

/** \brief Mask for Ifx_GETH_DMA_DEBUG_STATUS1_Bits.TPS3 */
#define IFX_GETH_DMA_DEBUG_STATUS1_TPS3_MSK (0xfu)

/** \brief Offset for Ifx_GETH_DMA_DEBUG_STATUS1_Bits.TPS3 */
#define IFX_GETH_DMA_DEBUG_STATUS1_TPS3_OFF (4u)

/** \brief Length for Ifx_GETH_DMA_CH_CONTROL_Bits.PBLx8 */
#define IFX_GETH_DMA_CH_CONTROL_PBLX8_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_CONTROL_Bits.PBLx8 */
#define IFX_GETH_DMA_CH_CONTROL_PBLX8_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_CONTROL_Bits.PBLx8 */
#define IFX_GETH_DMA_CH_CONTROL_PBLX8_OFF (16u)

/** \brief Length for Ifx_GETH_DMA_CH_CONTROL_Bits.DSL */
#define IFX_GETH_DMA_CH_CONTROL_DSL_LEN (3u)

/** \brief Mask for Ifx_GETH_DMA_CH_CONTROL_Bits.DSL */
#define IFX_GETH_DMA_CH_CONTROL_DSL_MSK (0x7u)

/** \brief Offset for Ifx_GETH_DMA_CH_CONTROL_Bits.DSL */
#define IFX_GETH_DMA_CH_CONTROL_DSL_OFF (18u)

/** \brief Length for Ifx_GETH_DMA_CH_CONTROL_Bits.SPH */
#define IFX_GETH_DMA_CH_CONTROL_SPH_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_CONTROL_Bits.SPH */
#define IFX_GETH_DMA_CH_CONTROL_SPH_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_CONTROL_Bits.SPH */
#define IFX_GETH_DMA_CH_CONTROL_SPH_OFF (24u)

/** \brief Length for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.ST */
#define IFX_GETH_DMA_CH_TX_CONTROL_ST_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.ST */
#define IFX_GETH_DMA_CH_TX_CONTROL_ST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.ST */
#define IFX_GETH_DMA_CH_TX_CONTROL_ST_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.TCW */
#define IFX_GETH_DMA_CH_TX_CONTROL_TCW_LEN (3u)

/** \brief Mask for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.TCW */
#define IFX_GETH_DMA_CH_TX_CONTROL_TCW_MSK (0x7u)

/** \brief Offset for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.TCW */
#define IFX_GETH_DMA_CH_TX_CONTROL_TCW_OFF (1u)

/** \brief Length for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.OSF */
#define IFX_GETH_DMA_CH_TX_CONTROL_OSF_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.OSF */
#define IFX_GETH_DMA_CH_TX_CONTROL_OSF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.OSF */
#define IFX_GETH_DMA_CH_TX_CONTROL_OSF_OFF (4u)

/** \brief Length for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.TxPBL */
#define IFX_GETH_DMA_CH_TX_CONTROL_TXPBL_LEN (6u)

/** \brief Mask for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.TxPBL */
#define IFX_GETH_DMA_CH_TX_CONTROL_TXPBL_MSK (0x3fu)

/** \brief Offset for Ifx_GETH_DMA_CH_TX_CONTROL_Bits.TxPBL */
#define IFX_GETH_DMA_CH_TX_CONTROL_TXPBL_OFF (16u)

/** \brief Length for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.SR */
#define IFX_GETH_DMA_CH_RX_CONTROL_SR_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.SR */
#define IFX_GETH_DMA_CH_RX_CONTROL_SR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.SR */
#define IFX_GETH_DMA_CH_RX_CONTROL_SR_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RBSZ_x_0 */
#define IFX_GETH_DMA_CH_RX_CONTROL_RBSZ_X_0_LEN (2u)

/** \brief Mask for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RBSZ_x_0 */
#define IFX_GETH_DMA_CH_RX_CONTROL_RBSZ_X_0_MSK (0x3u)

/** \brief Offset for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RBSZ_x_0 */
#define IFX_GETH_DMA_CH_RX_CONTROL_RBSZ_X_0_OFF (1u)

/** \brief Length for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RBSZ_13_y */
#define IFX_GETH_DMA_CH_RX_CONTROL_RBSZ_13_Y_LEN (12u)

/** \brief Mask for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RBSZ_13_y */
#define IFX_GETH_DMA_CH_RX_CONTROL_RBSZ_13_Y_MSK (0xfffu)

/** \brief Offset for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RBSZ_13_y */
#define IFX_GETH_DMA_CH_RX_CONTROL_RBSZ_13_Y_OFF (3u)

/** \brief Length for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RxPBL */
#define IFX_GETH_DMA_CH_RX_CONTROL_RXPBL_LEN (6u)

/** \brief Mask for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RxPBL */
#define IFX_GETH_DMA_CH_RX_CONTROL_RXPBL_MSK (0x3fu)

/** \brief Offset for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RxPBL */
#define IFX_GETH_DMA_CH_RX_CONTROL_RXPBL_OFF (16u)

/** \brief Length for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RPF */
#define IFX_GETH_DMA_CH_RX_CONTROL_RPF_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RPF */
#define IFX_GETH_DMA_CH_RX_CONTROL_RPF_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_RX_CONTROL_Bits.RPF */
#define IFX_GETH_DMA_CH_RX_CONTROL_RPF_OFF (31u)

/** \brief Length for Ifx_GETH_DMA_CH_TXDESC_LIST_ADDRESS_Bits.TDESLA */
#define IFX_GETH_DMA_CH_TXDESC_LIST_ADDRESS_TDESLA_LEN (30u)

/** \brief Mask for Ifx_GETH_DMA_CH_TXDESC_LIST_ADDRESS_Bits.TDESLA */
#define IFX_GETH_DMA_CH_TXDESC_LIST_ADDRESS_TDESLA_MSK (0x3fffffffu)

/** \brief Offset for Ifx_GETH_DMA_CH_TXDESC_LIST_ADDRESS_Bits.TDESLA */
#define IFX_GETH_DMA_CH_TXDESC_LIST_ADDRESS_TDESLA_OFF (2u)

/** \brief Length for Ifx_GETH_DMA_CH_RXDESC_LIST_ADDRESS_Bits.RDESLA */
#define IFX_GETH_DMA_CH_RXDESC_LIST_ADDRESS_RDESLA_LEN (30u)

/** \brief Mask for Ifx_GETH_DMA_CH_RXDESC_LIST_ADDRESS_Bits.RDESLA */
#define IFX_GETH_DMA_CH_RXDESC_LIST_ADDRESS_RDESLA_MSK (0x3fffffffu)

/** \brief Offset for Ifx_GETH_DMA_CH_RXDESC_LIST_ADDRESS_Bits.RDESLA */
#define IFX_GETH_DMA_CH_RXDESC_LIST_ADDRESS_RDESLA_OFF (2u)

/** \brief Length for Ifx_GETH_DMA_CH_TXDESC_TAIL_POINTER_Bits.TDTP */
#define IFX_GETH_DMA_CH_TXDESC_TAIL_POINTER_TDTP_LEN (30u)

/** \brief Mask for Ifx_GETH_DMA_CH_TXDESC_TAIL_POINTER_Bits.TDTP */
#define IFX_GETH_DMA_CH_TXDESC_TAIL_POINTER_TDTP_MSK (0x3fffffffu)

/** \brief Offset for Ifx_GETH_DMA_CH_TXDESC_TAIL_POINTER_Bits.TDTP */
#define IFX_GETH_DMA_CH_TXDESC_TAIL_POINTER_TDTP_OFF (2u)

/** \brief Length for Ifx_GETH_DMA_CH_RXDESC_TAIL_POINTER_Bits.RDTP */
#define IFX_GETH_DMA_CH_RXDESC_TAIL_POINTER_RDTP_LEN (30u)

/** \brief Mask for Ifx_GETH_DMA_CH_RXDESC_TAIL_POINTER_Bits.RDTP */
#define IFX_GETH_DMA_CH_RXDESC_TAIL_POINTER_RDTP_MSK (0x3fffffffu)

/** \brief Offset for Ifx_GETH_DMA_CH_RXDESC_TAIL_POINTER_Bits.RDTP */
#define IFX_GETH_DMA_CH_RXDESC_TAIL_POINTER_RDTP_OFF (2u)

/** \brief Length for Ifx_GETH_DMA_CH_TXDESC_RING_LENGTH_Bits.TDRL */
#define IFX_GETH_DMA_CH_TXDESC_RING_LENGTH_TDRL_LEN (10u)

/** \brief Mask for Ifx_GETH_DMA_CH_TXDESC_RING_LENGTH_Bits.TDRL */
#define IFX_GETH_DMA_CH_TXDESC_RING_LENGTH_TDRL_MSK (0x3ffu)

/** \brief Offset for Ifx_GETH_DMA_CH_TXDESC_RING_LENGTH_Bits.TDRL */
#define IFX_GETH_DMA_CH_TXDESC_RING_LENGTH_TDRL_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_RXDESC_RING_LENGTH_Bits.RDRL */
#define IFX_GETH_DMA_CH_RXDESC_RING_LENGTH_RDRL_LEN (10u)

/** \brief Mask for Ifx_GETH_DMA_CH_RXDESC_RING_LENGTH_Bits.RDRL */
#define IFX_GETH_DMA_CH_RXDESC_RING_LENGTH_RDRL_MSK (0x3ffu)

/** \brief Offset for Ifx_GETH_DMA_CH_RXDESC_RING_LENGTH_Bits.RDRL */
#define IFX_GETH_DMA_CH_RXDESC_RING_LENGTH_RDRL_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.TIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_TIE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.TIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_TIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.TIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_TIE_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.TXSE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_TXSE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.TXSE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_TXSE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.TXSE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_TXSE_OFF (1u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.TBUE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_TBUE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.TBUE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_TBUE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.TBUE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_TBUE_OFF (2u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RIE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RIE_OFF (6u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RBUE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RBUE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RBUE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RBUE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RBUE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RBUE_OFF (7u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RSE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RSE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RSE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RSE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RSE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RSE_OFF (8u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RWTE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RWTE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RWTE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RWTE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.RWTE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_RWTE_OFF (9u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.ETIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_ETIE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.ETIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_ETIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.ETIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_ETIE_OFF (10u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.ERIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_ERIE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.ERIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_ERIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.ERIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_ERIE_OFF (11u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.FBEE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_FBEE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.FBEE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_FBEE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.FBEE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_FBEE_OFF (12u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.CDEE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_CDEE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.CDEE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_CDEE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.CDEE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_CDEE_OFF (13u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.AIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_AIE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.AIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_AIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.AIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_AIE_OFF (14u)

/** \brief Length for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.NIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_NIE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.NIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_NIE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_INTERRUPT_ENABLE_Bits.NIE */
#define IFX_GETH_DMA_CH_INTERRUPT_ENABLE_NIE_OFF (15u)

/** \brief Length for Ifx_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_Bits.RWT */
#define IFX_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_RWT_LEN (8u)

/** \brief Mask for Ifx_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_Bits.RWT */
#define IFX_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MSK (0xffu)

/** \brief Offset for Ifx_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_Bits.RWT */
#define IFX_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_RWT_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_Bits.RWTU */
#define IFX_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_LEN (2u)

/** \brief Mask for Ifx_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_Bits.RWTU */
#define IFX_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MSK (0x3u)

/** \brief Offset for Ifx_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_Bits.RWTU */
#define IFX_GETH_DMA_CH_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_OFF (16u)

/** \brief Length for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.ESC */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_ESC_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.ESC */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_ESC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.ESC */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_ESC_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.ASC */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_ASC_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.ASC */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_ASC_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.ASC */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_ASC_OFF (1u)

/** \brief Length for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.SIV */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_SIV_LEN (12u)

/** \brief Mask for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.SIV */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_SIV_MSK (0xfffu)

/** \brief Offset for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.SIV */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_SIV_OFF (4u)

/** \brief Length for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.RSN */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_RSN_LEN (4u)

/** \brief Mask for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.RSN */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_RSN_MSK (0xfu)

/** \brief Offset for Ifx_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_Bits.RSN */
#define IFX_GETH_DMA_CH_SLOT_FUNCTION_CONTROL_STATUS_RSN_OFF (16u)

/** \brief Length for Ifx_GETH_DMA_CH_CURRENT_APP_TXDESC_Bits.CURTDESAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_TXDESC_CURTDESAPTR_LEN (32u)

/** \brief Mask for Ifx_GETH_DMA_CH_CURRENT_APP_TXDESC_Bits.CURTDESAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_TXDESC_CURTDESAPTR_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_DMA_CH_CURRENT_APP_TXDESC_Bits.CURTDESAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_TXDESC_CURTDESAPTR_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_CURRENT_APP_RXDESC_Bits.CURRDESAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_RXDESC_CURRDESAPTR_LEN (32u)

/** \brief Mask for Ifx_GETH_DMA_CH_CURRENT_APP_RXDESC_Bits.CURRDESAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_RXDESC_CURRDESAPTR_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_DMA_CH_CURRENT_APP_RXDESC_Bits.CURRDESAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_RXDESC_CURRDESAPTR_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_CURRENT_APP_TXBUFFER_Bits.CURTBUFAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_TXBUFFER_CURTBUFAPTR_LEN (32u)

/** \brief Mask for Ifx_GETH_DMA_CH_CURRENT_APP_TXBUFFER_Bits.CURTBUFAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_DMA_CH_CURRENT_APP_TXBUFFER_Bits.CURTBUFAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_TXBUFFER_CURTBUFAPTR_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_CURRENT_APP_RXBUFFER_Bits.CURRBUFAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_RXBUFFER_CURRBUFAPTR_LEN (32u)

/** \brief Mask for Ifx_GETH_DMA_CH_CURRENT_APP_RXBUFFER_Bits.CURRBUFAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MSK (0xffffffffu)

/** \brief Offset for Ifx_GETH_DMA_CH_CURRENT_APP_RXBUFFER_Bits.CURRBUFAPTR */
#define IFX_GETH_DMA_CH_CURRENT_APP_RXBUFFER_CURRBUFAPTR_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.TI */
#define IFX_GETH_DMA_CH_STATUS_TI_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.TI */
#define IFX_GETH_DMA_CH_STATUS_TI_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.TI */
#define IFX_GETH_DMA_CH_STATUS_TI_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.TPS */
#define IFX_GETH_DMA_CH_STATUS_TPS_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.TPS */
#define IFX_GETH_DMA_CH_STATUS_TPS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.TPS */
#define IFX_GETH_DMA_CH_STATUS_TPS_OFF (1u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.TBU */
#define IFX_GETH_DMA_CH_STATUS_TBU_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.TBU */
#define IFX_GETH_DMA_CH_STATUS_TBU_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.TBU */
#define IFX_GETH_DMA_CH_STATUS_TBU_OFF (2u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.RI */
#define IFX_GETH_DMA_CH_STATUS_RI_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.RI */
#define IFX_GETH_DMA_CH_STATUS_RI_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.RI */
#define IFX_GETH_DMA_CH_STATUS_RI_OFF (6u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.RBU */
#define IFX_GETH_DMA_CH_STATUS_RBU_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.RBU */
#define IFX_GETH_DMA_CH_STATUS_RBU_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.RBU */
#define IFX_GETH_DMA_CH_STATUS_RBU_OFF (7u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.RPS */
#define IFX_GETH_DMA_CH_STATUS_RPS_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.RPS */
#define IFX_GETH_DMA_CH_STATUS_RPS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.RPS */
#define IFX_GETH_DMA_CH_STATUS_RPS_OFF (8u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.RWT */
#define IFX_GETH_DMA_CH_STATUS_RWT_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.RWT */
#define IFX_GETH_DMA_CH_STATUS_RWT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.RWT */
#define IFX_GETH_DMA_CH_STATUS_RWT_OFF (9u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.ETI */
#define IFX_GETH_DMA_CH_STATUS_ETI_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.ETI */
#define IFX_GETH_DMA_CH_STATUS_ETI_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.ETI */
#define IFX_GETH_DMA_CH_STATUS_ETI_OFF (10u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.ERI */
#define IFX_GETH_DMA_CH_STATUS_ERI_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.ERI */
#define IFX_GETH_DMA_CH_STATUS_ERI_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.ERI */
#define IFX_GETH_DMA_CH_STATUS_ERI_OFF (11u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.FBE */
#define IFX_GETH_DMA_CH_STATUS_FBE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.FBE */
#define IFX_GETH_DMA_CH_STATUS_FBE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.FBE */
#define IFX_GETH_DMA_CH_STATUS_FBE_OFF (12u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.CDE */
#define IFX_GETH_DMA_CH_STATUS_CDE_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.CDE */
#define IFX_GETH_DMA_CH_STATUS_CDE_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.CDE */
#define IFX_GETH_DMA_CH_STATUS_CDE_OFF (13u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.AIS */
#define IFX_GETH_DMA_CH_STATUS_AIS_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.AIS */
#define IFX_GETH_DMA_CH_STATUS_AIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.AIS */
#define IFX_GETH_DMA_CH_STATUS_AIS_OFF (14u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.NIS */
#define IFX_GETH_DMA_CH_STATUS_NIS_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.NIS */
#define IFX_GETH_DMA_CH_STATUS_NIS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.NIS */
#define IFX_GETH_DMA_CH_STATUS_NIS_OFF (15u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.TEB */
#define IFX_GETH_DMA_CH_STATUS_TEB_LEN (3u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.TEB */
#define IFX_GETH_DMA_CH_STATUS_TEB_MSK (0x7u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.TEB */
#define IFX_GETH_DMA_CH_STATUS_TEB_OFF (16u)

/** \brief Length for Ifx_GETH_DMA_CH_STATUS_Bits.REB */
#define IFX_GETH_DMA_CH_STATUS_REB_LEN (3u)

/** \brief Mask for Ifx_GETH_DMA_CH_STATUS_Bits.REB */
#define IFX_GETH_DMA_CH_STATUS_REB_MSK (0x7u)

/** \brief Offset for Ifx_GETH_DMA_CH_STATUS_Bits.REB */
#define IFX_GETH_DMA_CH_STATUS_REB_OFF (19u)

/** \brief Length for Ifx_GETH_DMA_CH_MISS_FRAME_CNT_Bits.MFC */
#define IFX_GETH_DMA_CH_MISS_FRAME_CNT_MFC_LEN (11u)

/** \brief Mask for Ifx_GETH_DMA_CH_MISS_FRAME_CNT_Bits.MFC */
#define IFX_GETH_DMA_CH_MISS_FRAME_CNT_MFC_MSK (0x7ffu)

/** \brief Offset for Ifx_GETH_DMA_CH_MISS_FRAME_CNT_Bits.MFC */
#define IFX_GETH_DMA_CH_MISS_FRAME_CNT_MFC_OFF (0u)

/** \brief Length for Ifx_GETH_DMA_CH_MISS_FRAME_CNT_Bits.MFCO */
#define IFX_GETH_DMA_CH_MISS_FRAME_CNT_MFCO_LEN (1u)

/** \brief Mask for Ifx_GETH_DMA_CH_MISS_FRAME_CNT_Bits.MFCO */
#define IFX_GETH_DMA_CH_MISS_FRAME_CNT_MFCO_MSK (0x1u)

/** \brief Offset for Ifx_GETH_DMA_CH_MISS_FRAME_CNT_Bits.MFCO */
#define IFX_GETH_DMA_CH_MISS_FRAME_CNT_MFCO_OFF (15u)

/** \brief Length for Ifx_GETH_CLC_Bits.DISR */
#define IFX_GETH_CLC_DISR_LEN (1u)

/** \brief Mask for Ifx_GETH_CLC_Bits.DISR */
#define IFX_GETH_CLC_DISR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_CLC_Bits.DISR */
#define IFX_GETH_CLC_DISR_OFF (0u)

/** \brief Length for Ifx_GETH_CLC_Bits.DISS */
#define IFX_GETH_CLC_DISS_LEN (1u)

/** \brief Mask for Ifx_GETH_CLC_Bits.DISS */
#define IFX_GETH_CLC_DISS_MSK (0x1u)

/** \brief Offset for Ifx_GETH_CLC_Bits.DISS */
#define IFX_GETH_CLC_DISS_OFF (1u)

/** \brief Length for Ifx_GETH_ID_Bits.MODREV */
#define IFX_GETH_ID_MODREV_LEN (8u)

/** \brief Mask for Ifx_GETH_ID_Bits.MODREV */
#define IFX_GETH_ID_MODREV_MSK (0xffu)

/** \brief Offset for Ifx_GETH_ID_Bits.MODREV */
#define IFX_GETH_ID_MODREV_OFF (0u)

/** \brief Length for Ifx_GETH_ID_Bits.MODTYPE */
#define IFX_GETH_ID_MODTYPE_LEN (8u)

/** \brief Mask for Ifx_GETH_ID_Bits.MODTYPE */
#define IFX_GETH_ID_MODTYPE_MSK (0xffu)

/** \brief Offset for Ifx_GETH_ID_Bits.MODTYPE */
#define IFX_GETH_ID_MODTYPE_OFF (8u)

/** \brief Length for Ifx_GETH_ID_Bits.MODNUM */
#define IFX_GETH_ID_MODNUM_LEN (16u)

/** \brief Mask for Ifx_GETH_ID_Bits.MODNUM */
#define IFX_GETH_ID_MODNUM_MSK (0xffffu)

/** \brief Offset for Ifx_GETH_ID_Bits.MODNUM */
#define IFX_GETH_ID_MODNUM_OFF (16u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.ALTI0 */
#define IFX_GETH_GPCTL_ALTI0_LEN (2u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.ALTI0 */
#define IFX_GETH_GPCTL_ALTI0_MSK (0x3u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.ALTI0 */
#define IFX_GETH_GPCTL_ALTI0_OFF (0u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.ALTI1 */
#define IFX_GETH_GPCTL_ALTI1_LEN (2u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.ALTI1 */
#define IFX_GETH_GPCTL_ALTI1_MSK (0x3u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.ALTI1 */
#define IFX_GETH_GPCTL_ALTI1_OFF (2u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.ALTI2 */
#define IFX_GETH_GPCTL_ALTI2_LEN (2u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.ALTI2 */
#define IFX_GETH_GPCTL_ALTI2_MSK (0x3u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.ALTI2 */
#define IFX_GETH_GPCTL_ALTI2_OFF (4u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.ALTI3 */
#define IFX_GETH_GPCTL_ALTI3_LEN (2u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.ALTI3 */
#define IFX_GETH_GPCTL_ALTI3_MSK (0x3u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.ALTI3 */
#define IFX_GETH_GPCTL_ALTI3_OFF (6u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.ALTI4 */
#define IFX_GETH_GPCTL_ALTI4_LEN (2u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.ALTI4 */
#define IFX_GETH_GPCTL_ALTI4_MSK (0x3u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.ALTI4 */
#define IFX_GETH_GPCTL_ALTI4_OFF (8u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.ALTI5 */
#define IFX_GETH_GPCTL_ALTI5_LEN (2u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.ALTI5 */
#define IFX_GETH_GPCTL_ALTI5_MSK (0x3u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.ALTI5 */
#define IFX_GETH_GPCTL_ALTI5_OFF (10u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.ALTI6 */
#define IFX_GETH_GPCTL_ALTI6_LEN (2u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.ALTI6 */
#define IFX_GETH_GPCTL_ALTI6_MSK (0x3u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.ALTI6 */
#define IFX_GETH_GPCTL_ALTI6_OFF (12u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.ALTI7 */
#define IFX_GETH_GPCTL_ALTI7_LEN (2u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.ALTI7 */
#define IFX_GETH_GPCTL_ALTI7_MSK (0x3u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.ALTI7 */
#define IFX_GETH_GPCTL_ALTI7_OFF (14u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.ALTI8 */
#define IFX_GETH_GPCTL_ALTI8_LEN (2u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.ALTI8 */
#define IFX_GETH_GPCTL_ALTI8_MSK (0x3u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.ALTI8 */
#define IFX_GETH_GPCTL_ALTI8_OFF (16u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.ALTI9 */
#define IFX_GETH_GPCTL_ALTI9_LEN (2u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.ALTI9 */
#define IFX_GETH_GPCTL_ALTI9_MSK (0x3u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.ALTI9 */
#define IFX_GETH_GPCTL_ALTI9_OFF (18u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.ALTI10 */
#define IFX_GETH_GPCTL_ALTI10_LEN (2u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.ALTI10 */
#define IFX_GETH_GPCTL_ALTI10_MSK (0x3u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.ALTI10 */
#define IFX_GETH_GPCTL_ALTI10_OFF (20u)

/** \brief Length for Ifx_GETH_GPCTL_Bits.EPR */
#define IFX_GETH_GPCTL_EPR_LEN (3u)

/** \brief Mask for Ifx_GETH_GPCTL_Bits.EPR */
#define IFX_GETH_GPCTL_EPR_MSK (0x7u)

/** \brief Offset for Ifx_GETH_GPCTL_Bits.EPR */
#define IFX_GETH_GPCTL_EPR_OFF (22u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN0 */
#define IFX_GETH_ACCEN0_EN0_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN0 */
#define IFX_GETH_ACCEN0_EN0_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN0 */
#define IFX_GETH_ACCEN0_EN0_OFF (0u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN1 */
#define IFX_GETH_ACCEN0_EN1_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN1 */
#define IFX_GETH_ACCEN0_EN1_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN1 */
#define IFX_GETH_ACCEN0_EN1_OFF (1u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN2 */
#define IFX_GETH_ACCEN0_EN2_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN2 */
#define IFX_GETH_ACCEN0_EN2_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN2 */
#define IFX_GETH_ACCEN0_EN2_OFF (2u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN3 */
#define IFX_GETH_ACCEN0_EN3_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN3 */
#define IFX_GETH_ACCEN0_EN3_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN3 */
#define IFX_GETH_ACCEN0_EN3_OFF (3u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN4 */
#define IFX_GETH_ACCEN0_EN4_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN4 */
#define IFX_GETH_ACCEN0_EN4_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN4 */
#define IFX_GETH_ACCEN0_EN4_OFF (4u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN5 */
#define IFX_GETH_ACCEN0_EN5_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN5 */
#define IFX_GETH_ACCEN0_EN5_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN5 */
#define IFX_GETH_ACCEN0_EN5_OFF (5u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN6 */
#define IFX_GETH_ACCEN0_EN6_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN6 */
#define IFX_GETH_ACCEN0_EN6_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN6 */
#define IFX_GETH_ACCEN0_EN6_OFF (6u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN7 */
#define IFX_GETH_ACCEN0_EN7_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN7 */
#define IFX_GETH_ACCEN0_EN7_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN7 */
#define IFX_GETH_ACCEN0_EN7_OFF (7u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN8 */
#define IFX_GETH_ACCEN0_EN8_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN8 */
#define IFX_GETH_ACCEN0_EN8_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN8 */
#define IFX_GETH_ACCEN0_EN8_OFF (8u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN9 */
#define IFX_GETH_ACCEN0_EN9_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN9 */
#define IFX_GETH_ACCEN0_EN9_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN9 */
#define IFX_GETH_ACCEN0_EN9_OFF (9u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN10 */
#define IFX_GETH_ACCEN0_EN10_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN10 */
#define IFX_GETH_ACCEN0_EN10_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN10 */
#define IFX_GETH_ACCEN0_EN10_OFF (10u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN11 */
#define IFX_GETH_ACCEN0_EN11_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN11 */
#define IFX_GETH_ACCEN0_EN11_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN11 */
#define IFX_GETH_ACCEN0_EN11_OFF (11u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN12 */
#define IFX_GETH_ACCEN0_EN12_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN12 */
#define IFX_GETH_ACCEN0_EN12_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN12 */
#define IFX_GETH_ACCEN0_EN12_OFF (12u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN13 */
#define IFX_GETH_ACCEN0_EN13_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN13 */
#define IFX_GETH_ACCEN0_EN13_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN13 */
#define IFX_GETH_ACCEN0_EN13_OFF (13u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN14 */
#define IFX_GETH_ACCEN0_EN14_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN14 */
#define IFX_GETH_ACCEN0_EN14_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN14 */
#define IFX_GETH_ACCEN0_EN14_OFF (14u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN15 */
#define IFX_GETH_ACCEN0_EN15_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN15 */
#define IFX_GETH_ACCEN0_EN15_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN15 */
#define IFX_GETH_ACCEN0_EN15_OFF (15u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN16 */
#define IFX_GETH_ACCEN0_EN16_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN16 */
#define IFX_GETH_ACCEN0_EN16_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN16 */
#define IFX_GETH_ACCEN0_EN16_OFF (16u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN17 */
#define IFX_GETH_ACCEN0_EN17_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN17 */
#define IFX_GETH_ACCEN0_EN17_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN17 */
#define IFX_GETH_ACCEN0_EN17_OFF (17u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN18 */
#define IFX_GETH_ACCEN0_EN18_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN18 */
#define IFX_GETH_ACCEN0_EN18_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN18 */
#define IFX_GETH_ACCEN0_EN18_OFF (18u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN19 */
#define IFX_GETH_ACCEN0_EN19_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN19 */
#define IFX_GETH_ACCEN0_EN19_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN19 */
#define IFX_GETH_ACCEN0_EN19_OFF (19u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN20 */
#define IFX_GETH_ACCEN0_EN20_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN20 */
#define IFX_GETH_ACCEN0_EN20_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN20 */
#define IFX_GETH_ACCEN0_EN20_OFF (20u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN21 */
#define IFX_GETH_ACCEN0_EN21_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN21 */
#define IFX_GETH_ACCEN0_EN21_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN21 */
#define IFX_GETH_ACCEN0_EN21_OFF (21u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN22 */
#define IFX_GETH_ACCEN0_EN22_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN22 */
#define IFX_GETH_ACCEN0_EN22_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN22 */
#define IFX_GETH_ACCEN0_EN22_OFF (22u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN23 */
#define IFX_GETH_ACCEN0_EN23_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN23 */
#define IFX_GETH_ACCEN0_EN23_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN23 */
#define IFX_GETH_ACCEN0_EN23_OFF (23u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN24 */
#define IFX_GETH_ACCEN0_EN24_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN24 */
#define IFX_GETH_ACCEN0_EN24_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN24 */
#define IFX_GETH_ACCEN0_EN24_OFF (24u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN25 */
#define IFX_GETH_ACCEN0_EN25_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN25 */
#define IFX_GETH_ACCEN0_EN25_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN25 */
#define IFX_GETH_ACCEN0_EN25_OFF (25u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN26 */
#define IFX_GETH_ACCEN0_EN26_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN26 */
#define IFX_GETH_ACCEN0_EN26_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN26 */
#define IFX_GETH_ACCEN0_EN26_OFF (26u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN27 */
#define IFX_GETH_ACCEN0_EN27_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN27 */
#define IFX_GETH_ACCEN0_EN27_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN27 */
#define IFX_GETH_ACCEN0_EN27_OFF (27u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN28 */
#define IFX_GETH_ACCEN0_EN28_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN28 */
#define IFX_GETH_ACCEN0_EN28_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN28 */
#define IFX_GETH_ACCEN0_EN28_OFF (28u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN29 */
#define IFX_GETH_ACCEN0_EN29_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN29 */
#define IFX_GETH_ACCEN0_EN29_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN29 */
#define IFX_GETH_ACCEN0_EN29_OFF (29u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN30 */
#define IFX_GETH_ACCEN0_EN30_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN30 */
#define IFX_GETH_ACCEN0_EN30_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN30 */
#define IFX_GETH_ACCEN0_EN30_OFF (30u)

/** \brief Length for Ifx_GETH_ACCEN0_Bits.EN31 */
#define IFX_GETH_ACCEN0_EN31_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEN0_Bits.EN31 */
#define IFX_GETH_ACCEN0_EN31_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEN0_Bits.EN31 */
#define IFX_GETH_ACCEN0_EN31_OFF (31u)

/** \brief Length for Ifx_GETH_KRST0_Bits.RST */
#define IFX_GETH_KRST0_RST_LEN (1u)

/** \brief Mask for Ifx_GETH_KRST0_Bits.RST */
#define IFX_GETH_KRST0_RST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_KRST0_Bits.RST */
#define IFX_GETH_KRST0_RST_OFF (0u)

/** \brief Length for Ifx_GETH_KRST0_Bits.RSTSTAT */
#define IFX_GETH_KRST0_RSTSTAT_LEN (1u)

/** \brief Mask for Ifx_GETH_KRST0_Bits.RSTSTAT */
#define IFX_GETH_KRST0_RSTSTAT_MSK (0x1u)

/** \brief Offset for Ifx_GETH_KRST0_Bits.RSTSTAT */
#define IFX_GETH_KRST0_RSTSTAT_OFF (1u)

/** \brief Length for Ifx_GETH_KRST1_Bits.RST */
#define IFX_GETH_KRST1_RST_LEN (1u)

/** \brief Mask for Ifx_GETH_KRST1_Bits.RST */
#define IFX_GETH_KRST1_RST_MSK (0x1u)

/** \brief Offset for Ifx_GETH_KRST1_Bits.RST */
#define IFX_GETH_KRST1_RST_OFF (0u)

/** \brief Length for Ifx_GETH_KRSTCLR_Bits.CLR */
#define IFX_GETH_KRSTCLR_CLR_LEN (1u)

/** \brief Mask for Ifx_GETH_KRSTCLR_Bits.CLR */
#define IFX_GETH_KRSTCLR_CLR_MSK (0x1u)

/** \brief Offset for Ifx_GETH_KRSTCLR_Bits.CLR */
#define IFX_GETH_KRSTCLR_CLR_OFF (0u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN0 */
#define IFX_GETH_ACCEND_ACCEN0D_EN0_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN0 */
#define IFX_GETH_ACCEND_ACCEN0D_EN0_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN0 */
#define IFX_GETH_ACCEND_ACCEN0D_EN0_OFF (0u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN1 */
#define IFX_GETH_ACCEND_ACCEN0D_EN1_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN1 */
#define IFX_GETH_ACCEND_ACCEN0D_EN1_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN1 */
#define IFX_GETH_ACCEND_ACCEN0D_EN1_OFF (1u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN2 */
#define IFX_GETH_ACCEND_ACCEN0D_EN2_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN2 */
#define IFX_GETH_ACCEND_ACCEN0D_EN2_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN2 */
#define IFX_GETH_ACCEND_ACCEN0D_EN2_OFF (2u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN3 */
#define IFX_GETH_ACCEND_ACCEN0D_EN3_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN3 */
#define IFX_GETH_ACCEND_ACCEN0D_EN3_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN3 */
#define IFX_GETH_ACCEND_ACCEN0D_EN3_OFF (3u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN4 */
#define IFX_GETH_ACCEND_ACCEN0D_EN4_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN4 */
#define IFX_GETH_ACCEND_ACCEN0D_EN4_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN4 */
#define IFX_GETH_ACCEND_ACCEN0D_EN4_OFF (4u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN5 */
#define IFX_GETH_ACCEND_ACCEN0D_EN5_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN5 */
#define IFX_GETH_ACCEND_ACCEN0D_EN5_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN5 */
#define IFX_GETH_ACCEND_ACCEN0D_EN5_OFF (5u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN6 */
#define IFX_GETH_ACCEND_ACCEN0D_EN6_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN6 */
#define IFX_GETH_ACCEND_ACCEN0D_EN6_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN6 */
#define IFX_GETH_ACCEND_ACCEN0D_EN6_OFF (6u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN7 */
#define IFX_GETH_ACCEND_ACCEN0D_EN7_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN7 */
#define IFX_GETH_ACCEND_ACCEN0D_EN7_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN7 */
#define IFX_GETH_ACCEND_ACCEN0D_EN7_OFF (7u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN8 */
#define IFX_GETH_ACCEND_ACCEN0D_EN8_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN8 */
#define IFX_GETH_ACCEND_ACCEN0D_EN8_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN8 */
#define IFX_GETH_ACCEND_ACCEN0D_EN8_OFF (8u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN9 */
#define IFX_GETH_ACCEND_ACCEN0D_EN9_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN9 */
#define IFX_GETH_ACCEND_ACCEN0D_EN9_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN9 */
#define IFX_GETH_ACCEND_ACCEN0D_EN9_OFF (9u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN10 */
#define IFX_GETH_ACCEND_ACCEN0D_EN10_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN10 */
#define IFX_GETH_ACCEND_ACCEN0D_EN10_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN10 */
#define IFX_GETH_ACCEND_ACCEN0D_EN10_OFF (10u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN11 */
#define IFX_GETH_ACCEND_ACCEN0D_EN11_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN11 */
#define IFX_GETH_ACCEND_ACCEN0D_EN11_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN11 */
#define IFX_GETH_ACCEND_ACCEN0D_EN11_OFF (11u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN12 */
#define IFX_GETH_ACCEND_ACCEN0D_EN12_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN12 */
#define IFX_GETH_ACCEND_ACCEN0D_EN12_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN12 */
#define IFX_GETH_ACCEND_ACCEN0D_EN12_OFF (12u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN13 */
#define IFX_GETH_ACCEND_ACCEN0D_EN13_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN13 */
#define IFX_GETH_ACCEND_ACCEN0D_EN13_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN13 */
#define IFX_GETH_ACCEND_ACCEN0D_EN13_OFF (13u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN14 */
#define IFX_GETH_ACCEND_ACCEN0D_EN14_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN14 */
#define IFX_GETH_ACCEND_ACCEN0D_EN14_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN14 */
#define IFX_GETH_ACCEND_ACCEN0D_EN14_OFF (14u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN15 */
#define IFX_GETH_ACCEND_ACCEN0D_EN15_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN15 */
#define IFX_GETH_ACCEND_ACCEN0D_EN15_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN15 */
#define IFX_GETH_ACCEND_ACCEN0D_EN15_OFF (15u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN16 */
#define IFX_GETH_ACCEND_ACCEN0D_EN16_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN16 */
#define IFX_GETH_ACCEND_ACCEN0D_EN16_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN16 */
#define IFX_GETH_ACCEND_ACCEN0D_EN16_OFF (16u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN17 */
#define IFX_GETH_ACCEND_ACCEN0D_EN17_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN17 */
#define IFX_GETH_ACCEND_ACCEN0D_EN17_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN17 */
#define IFX_GETH_ACCEND_ACCEN0D_EN17_OFF (17u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN18 */
#define IFX_GETH_ACCEND_ACCEN0D_EN18_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN18 */
#define IFX_GETH_ACCEND_ACCEN0D_EN18_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN18 */
#define IFX_GETH_ACCEND_ACCEN0D_EN18_OFF (18u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN19 */
#define IFX_GETH_ACCEND_ACCEN0D_EN19_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN19 */
#define IFX_GETH_ACCEND_ACCEN0D_EN19_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN19 */
#define IFX_GETH_ACCEND_ACCEN0D_EN19_OFF (19u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN20 */
#define IFX_GETH_ACCEND_ACCEN0D_EN20_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN20 */
#define IFX_GETH_ACCEND_ACCEN0D_EN20_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN20 */
#define IFX_GETH_ACCEND_ACCEN0D_EN20_OFF (20u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN21 */
#define IFX_GETH_ACCEND_ACCEN0D_EN21_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN21 */
#define IFX_GETH_ACCEND_ACCEN0D_EN21_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN21 */
#define IFX_GETH_ACCEND_ACCEN0D_EN21_OFF (21u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN22 */
#define IFX_GETH_ACCEND_ACCEN0D_EN22_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN22 */
#define IFX_GETH_ACCEND_ACCEN0D_EN22_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN22 */
#define IFX_GETH_ACCEND_ACCEN0D_EN22_OFF (22u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN23 */
#define IFX_GETH_ACCEND_ACCEN0D_EN23_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN23 */
#define IFX_GETH_ACCEND_ACCEN0D_EN23_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN23 */
#define IFX_GETH_ACCEND_ACCEN0D_EN23_OFF (23u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN24 */
#define IFX_GETH_ACCEND_ACCEN0D_EN24_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN24 */
#define IFX_GETH_ACCEND_ACCEN0D_EN24_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN24 */
#define IFX_GETH_ACCEND_ACCEN0D_EN24_OFF (24u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN25 */
#define IFX_GETH_ACCEND_ACCEN0D_EN25_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN25 */
#define IFX_GETH_ACCEND_ACCEN0D_EN25_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN25 */
#define IFX_GETH_ACCEND_ACCEN0D_EN25_OFF (25u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN26 */
#define IFX_GETH_ACCEND_ACCEN0D_EN26_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN26 */
#define IFX_GETH_ACCEND_ACCEN0D_EN26_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN26 */
#define IFX_GETH_ACCEND_ACCEN0D_EN26_OFF (26u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN27 */
#define IFX_GETH_ACCEND_ACCEN0D_EN27_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN27 */
#define IFX_GETH_ACCEND_ACCEN0D_EN27_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN27 */
#define IFX_GETH_ACCEND_ACCEN0D_EN27_OFF (27u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN28 */
#define IFX_GETH_ACCEND_ACCEN0D_EN28_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN28 */
#define IFX_GETH_ACCEND_ACCEN0D_EN28_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN28 */
#define IFX_GETH_ACCEND_ACCEN0D_EN28_OFF (28u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN29 */
#define IFX_GETH_ACCEND_ACCEN0D_EN29_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN29 */
#define IFX_GETH_ACCEND_ACCEN0D_EN29_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN29 */
#define IFX_GETH_ACCEND_ACCEN0D_EN29_OFF (29u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN30 */
#define IFX_GETH_ACCEND_ACCEN0D_EN30_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN30 */
#define IFX_GETH_ACCEND_ACCEN0D_EN30_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN30 */
#define IFX_GETH_ACCEND_ACCEN0D_EN30_OFF (30u)

/** \brief Length for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN31 */
#define IFX_GETH_ACCEND_ACCEN0D_EN31_LEN (1u)

/** \brief Mask for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN31 */
#define IFX_GETH_ACCEND_ACCEN0D_EN31_MSK (0x1u)

/** \brief Offset for Ifx_GETH_ACCEND_ACCEN0D_Bits.EN31 */
#define IFX_GETH_ACCEND_ACCEN0D_EN31_OFF (31u)

/** \brief Length for Ifx_GETH_SKEWCTL_Bits.TXCFG */
#define IFX_GETH_SKEWCTL_TXCFG_LEN (4u)

/** \brief Mask for Ifx_GETH_SKEWCTL_Bits.TXCFG */
#define IFX_GETH_SKEWCTL_TXCFG_MSK (0xfu)

/** \brief Offset for Ifx_GETH_SKEWCTL_Bits.TXCFG */
#define IFX_GETH_SKEWCTL_TXCFG_OFF (0u)

/** \brief Length for Ifx_GETH_SKEWCTL_Bits.RXCFG */
#define IFX_GETH_SKEWCTL_RXCFG_LEN (4u)

/** \brief Mask for Ifx_GETH_SKEWCTL_Bits.RXCFG */
#define IFX_GETH_SKEWCTL_RXCFG_MSK (0xfu)

/** \brief Offset for Ifx_GETH_SKEWCTL_Bits.RXCFG */
#define IFX_GETH_SKEWCTL_RXCFG_OFF (8u)

/** \}  */

/******************************************************************************/

/******************************************************************************/

#endif /* IFXGETH_BF_H */
